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Searched refs:getOperand (Results 1 – 25 of 437) sorted by relevance

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/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp38 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
39 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
40 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
41 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask); in EmitAnyX86InstComments()
46 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
47 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
48 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
54 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
55 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
56 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
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/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp81 switch (MI->getOperand(0).getImm()) { in printInst()
103 const MCOperand &Dst = MI->getOperand(0); in printInst()
104 const MCOperand &MO1 = MI->getOperand(1); in printInst()
105 const MCOperand &MO2 = MI->getOperand(2); in printInst()
106 const MCOperand &MO3 = MI->getOperand(3); in printInst()
126 const MCOperand &Dst = MI->getOperand(0); in printInst()
127 const MCOperand &MO1 = MI->getOperand(1); in printInst()
128 const MCOperand &MO2 = MI->getOperand(2); in printInst()
155 MI->getOperand(0).getReg() == ARM::SP && in printInst()
167 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP && in printInst()
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/external/llvm/lib/Transforms/InstCombine/
DInstCombineVectorOps.cpp40 isa<ConstantInt>(I->getOperand(2))) in CheapToScalarize()
46 (CheapToScalarize(BO->getOperand(0), isConstant) || in CheapToScalarize()
47 CheapToScalarize(BO->getOperand(1), isConstant))) in CheapToScalarize()
51 (CheapToScalarize(CI->getOperand(0), isConstant) || in CheapToScalarize()
52 CheapToScalarize(CI->getOperand(1), isConstant))) in CheapToScalarize()
73 if (!isa<ConstantInt>(III->getOperand(2))) in FindScalarElement()
75 unsigned IIElt = cast<ConstantInt>(III->getOperand(2))->getZExtValue(); in FindScalarElement()
80 return III->getOperand(1); in FindScalarElement()
84 return FindScalarElement(III->getOperand(0), EltNo); in FindScalarElement()
88 unsigned LHSWidth = SVI->getOperand(0)->getType()->getVectorNumElements(); in FindScalarElement()
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DInstCombineShifts.cpp23 assert(I.getOperand(1)->getType() == I.getOperand(0)->getType()); in commonShiftTransforms()
24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in commonShiftTransforms()
92 if (MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
95 return CanEvaluateTruncated(I->getOperand(0), Ty); in CanEvaluateShifted()
112 return CanEvaluateShifted(I->getOperand(0), NumBits, isLeftShift, IC) && in CanEvaluateShifted()
113 CanEvaluateShifted(I->getOperand(1), NumBits, isLeftShift, IC); in CanEvaluateShifted()
117 CI = dyn_cast<ConstantInt>(I->getOperand(1)); in CanEvaluateShifted()
132 if (MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
141 CI = dyn_cast<ConstantInt>(I->getOperand(1)); in CanEvaluateShifted()
156 if (MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
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DInstCombineSelect.cpp32 LHS = ICI->getOperand(0); in MatchSelectPattern()
33 RHS = ICI->getOperand(1); in MatchSelectPattern()
36 if (SI->getTrueValue() == ICI->getOperand(0) && in MatchSelectPattern()
37 SI->getFalseValue() == ICI->getOperand(1)) { in MatchSelectPattern()
52 if (SI->getTrueValue() == ICI->getOperand(1) && in MatchSelectPattern()
53 SI->getFalseValue() == ICI->getOperand(0)) { in MatchSelectPattern()
130 if (TI->getOperand(0)->getType() != FI->getOperand(0)->getType()) in FoldSelectOpOp()
136 FI->getOperand(0)->getType()->getVectorNumElements()) in FoldSelectOpOp()
143 Value *NewSI = Builder->CreateSelect(SI.getCondition(), TI->getOperand(0), in FoldSelectOpOp()
144 FI->getOperand(0), SI.getName()+".v"); in FoldSelectOpOp()
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DInstCombineSimplifyDemanded.cpp34 ConstantInt *OpC = dyn_cast<ConstantInt>(I->getOperand(OpNo)); in ShrinkDemandedConstant()
160 ComputeMaskedBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth+1); in SimplifyDemandedUseBits()
161 ComputeMaskedBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1); in SimplifyDemandedUseBits()
168 return I->getOperand(0); in SimplifyDemandedUseBits()
171 return I->getOperand(1); in SimplifyDemandedUseBits()
182 ComputeMaskedBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth+1); in SimplifyDemandedUseBits()
183 ComputeMaskedBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1); in SimplifyDemandedUseBits()
190 return I->getOperand(0); in SimplifyDemandedUseBits()
193 return I->getOperand(1); in SimplifyDemandedUseBits()
199 return I->getOperand(0); in SimplifyDemandedUseBits()
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DInstCombineCasts.cpp43 if (ConstantInt *RHS = dyn_cast<ConstantInt>(I->getOperand(1))) { in DecomposeSimpleLinearExpr()
48 return I->getOperand(0); in DecomposeSimpleLinearExpr()
55 return I->getOperand(0); in DecomposeSimpleLinearExpr()
63 DecomposeSimpleLinearExpr(I->getOperand(0), SubScale, Offset); in DecomposeSimpleLinearExpr()
118 DecomposeSimpleLinearExpr(AI.getOperand(0), ArraySizeScale, ArrayOffset); in PromoteCastOfAllocation()
186 Value *LHS = EvaluateInDifferentType(I->getOperand(0), Ty, isSigned); in EvaluateInDifferentType()
187 Value *RHS = EvaluateInDifferentType(I->getOperand(1), Ty, isSigned); in EvaluateInDifferentType()
197 if (I->getOperand(0)->getType() == Ty) in EvaluateInDifferentType()
198 return I->getOperand(0); in EvaluateInDifferentType()
202 Res = CastInst::CreateIntegerCast(I->getOperand(0), Ty, in EvaluateInDifferentType()
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DInstCombineAndOrXor.cpp135 Value *X = Op->getOperand(0); in OptAndOp()
259 Value *ShVal = Op->getOperand(0); in OptAndOp()
349 !isa<ConstantInt>(LHSI->getOperand(1))) return 0; in FoldLogicalPlusAnd()
351 ConstantInt *N = cast<ConstantInt>(LHSI->getOperand(1)); in FoldLogicalPlusAnd()
386 return Builder->CreateSub(LHSI->getOperand(0), RHS, "fold"); in FoldLogicalPlusAnd()
387 return Builder->CreateAdd(LHSI->getOperand(0), RHS, "fold"); in FoldLogicalPlusAnd()
502 if (ConstantInt *C = dyn_cast<ConstantInt>(I->getOperand(1))) in decomposeBitTestICmp()
504 X = I->getOperand(0); in decomposeBitTestICmp()
514 if (ConstantInt *C = dyn_cast<ConstantInt>(I->getOperand(1))) in decomposeBitTestICmp()
516 X = I->getOperand(0); in decomposeBitTestICmp()
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/external/llvm/lib/Target/XCore/
DXCoreISelDAGToDAG.cpp101 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) in SelectADDRspii()
102 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRspii()
116 Base = Addr.getOperand(0); in SelectADDRdpii()
122 if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper) in SelectADDRdpii()
123 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRdpii()
126 Base = Addr.getOperand(0).getOperand(0); in SelectADDRdpii()
137 Base = Addr.getOperand(0); in SelectADDRcpii()
143 if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper) in SelectADDRcpii()
144 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRcpii()
147 Base = Addr.getOperand(0).getOperand(0); in SelectADDRcpii()
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/external/llvm/lib/Target/R600/
DR600ISelLowering.cpp112 MI->getOperand(0).getReg(), in EmitInstrWithCustomInserter()
113 MI->getOperand(1).getReg()); in EmitInstrWithCustomInserter()
121 MI->getOperand(0).getReg(), in EmitInstrWithCustomInserter()
122 MI->getOperand(1).getReg()); in EmitInstrWithCustomInserter()
130 MI->getOperand(0).getReg(), in EmitInstrWithCustomInserter()
131 MI->getOperand(1).getReg()); in EmitInstrWithCustomInserter()
137 unsigned maskedRegister = MI->getOperand(0).getReg(); in EmitInstrWithCustomInserter()
145 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(), in EmitInstrWithCustomInserter()
146 MI->getOperand(1).getFPImm()->getValueAPF() in EmitInstrWithCustomInserter()
150 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(), in EmitInstrWithCustomInserter()
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/external/llvm/unittests/IR/
DMDBuilderTest.cpp38 Value *Op = MD1->getOperand(0); in TEST_F()
52 EXPECT_TRUE(isa<ConstantInt>(R1->getOperand(0))); in TEST_F()
53 EXPECT_TRUE(isa<ConstantInt>(R1->getOperand(1))); in TEST_F()
54 ConstantInt *C0 = cast<ConstantInt>(R1->getOperand(0)); in TEST_F()
55 ConstantInt *C1 = cast<ConstantInt>(R1->getOperand(1)); in TEST_F()
66 EXPECT_EQ(R0->getOperand(0), R0); in TEST_F()
67 EXPECT_EQ(R1->getOperand(0), R1); in TEST_F()
68 EXPECT_TRUE(R0->getNumOperands() == 1 || R0->getOperand(1) == 0); in TEST_F()
69 EXPECT_TRUE(R1->getNumOperands() == 1 || R1->getOperand(1) == 0); in TEST_F()
77 EXPECT_TRUE(isa<MDString>(R0->getOperand(0))); in TEST_F()
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/external/llvm/lib/Target/Hexagon/
DHexagonSplitTFRCondSets.cpp90 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction()
91 int SrcReg1 = MI->getOperand(2).getReg(); in runOnMachineFunction()
92 int SrcReg2 = MI->getOperand(3).getReg(); in runOnMachineFunction()
108 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); in runOnMachineFunction()
112 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); in runOnMachineFunction()
120 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction()
121 int SrcReg1 = MI->getOperand(2).getReg(); in runOnMachineFunction()
128 addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); in runOnMachineFunction()
133 addReg(MI->getOperand(1).getReg()). in runOnMachineFunction()
134 addImm(MI->getOperand(3).getImm()); in runOnMachineFunction()
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DHexagonNewValueJump.cpp131 if (II->getOperand(i).isReg() && in canBeFeederToNewValueJump()
132 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { in canBeFeederToNewValueJump()
135 unsigned Reg = II->getOperand(i).getReg(); in canBeFeederToNewValueJump()
210 int64_t v = MI->getOperand(2).getImm(); in canCompareBeNewValueJump()
224 cmpReg1 = MI->getOperand(1).getReg(); in canCompareBeNewValueJump()
227 cmpOp2 = MI->getOperand(2).getReg(); in canCompareBeNewValueJump()
406 predReg = MI->getOperand(0).getReg(); in runOnMachineFunction()
435 jmpTarget = MI->getOperand(1).getMBB(); in runOnMachineFunction()
453 MI->getOperand(0).isReg() && in runOnMachineFunction()
454 MI->getOperand(0).getReg() == predReg) { in runOnMachineFunction()
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/external/llvm/lib/Target/PowerPC/InstPrinter/
DPPCInstPrinter.cpp34 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
35 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
36 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
57 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { in printInst()
67 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
68 unsigned char ME = MI->getOperand(3).getImm(); in printInst()
89 unsigned Code = MI->getOperand(OpNo).getImm(); in printPredicateOperand()
91 unsigned CCReg = MI->getOperand(OpNo+1).getReg(); in printPredicateOperand()
139 int Value = MI->getOperand(OpNo).getImm(); in printS5ImmOperand()
146 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU5ImmOperand()
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/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp426 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, in isNegatibleForFree()
430 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, in isNegatibleForFree()
444 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, in isNegatibleForFree()
448 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, in isNegatibleForFree()
454 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, in isNegatibleForFree()
464 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); in GetNegatedExpression()
482 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, in GetNegatedExpression()
486 GetNegatedExpression(Op.getOperand(0), DAG, in GetNegatedExpression()
488 Op.getOperand(1)); in GetNegatedExpression()
491 GetNegatedExpression(Op.getOperand(1), DAG, in GetNegatedExpression()
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DTargetLowering.cpp273 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); in ShrinkDemandedConstant()
283 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), in ShrinkDemandedConstant()
330 Op.getNode()->getOperand(0)), in ShrinkDemandedOp()
332 Op.getNode()->getOperand(1))); in ShrinkDemandedOp()
396 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { in SimplifyDemandedBits()
399 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth); in SimplifyDemandedBits()
402 return TLO.CombineTo(Op, Op.getOperand(0)); in SimplifyDemandedBits()
409 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, in SimplifyDemandedBits()
413 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, in SimplifyDemandedBits()
421 return TLO.CombineTo(Op, Op.getOperand(0)); in SimplifyDemandedBits()
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DLegalizeIntegerTypes.cpp155 SDValue Op = SExtPromotedInteger(N->getOperand(0)); in PromoteIntRes_AssertSext()
157 Op.getValueType(), Op, N->getOperand(1)); in PromoteIntRes_AssertSext()
162 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); in PromoteIntRes_AssertZext()
164 Op.getValueType(), Op, N->getOperand(1)); in PromoteIntRes_AssertZext()
181 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); in PromoteIntRes_Atomic1()
194 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); in PromoteIntRes_Atomic2()
195 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); in PromoteIntRes_Atomic2()
207 SDValue InOp = N->getOperand(0); in PromoteIntRes_BITCAST()
238 GetSplitVector(N->getOperand(0), Lo, Hi); in PromoteIntRes_BITCAST()
264 SDValue Op = GetPromotedInteger(N->getOperand(0)); in PromoteIntRes_BSWAP()
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/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp4189 Inst.addOperand(Inst.getOperand(0)); in cvtThumbMultiply()
5250 unsigned OpReg = Inst.getOperand(i).getReg(); in checkLowRegisterList()
5264 unsigned OpReg = Inst.getOperand(i).getReg(); in listContainsReg()
5301 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); in validateInstruction()
5317 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != in validateInstruction()
5327 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction()
5328 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction()
5336 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction()
5337 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction()
5346 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction()
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/external/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp85 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { in SelectADDRri()
88 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { in SelectADDRri()
92 Base = Addr.getOperand(0); in SelectADDRri()
98 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { in SelectADDRri()
99 Base = Addr.getOperand(1); in SelectADDRri()
100 Offset = Addr.getOperand(0).getOperand(0); in SelectADDRri()
103 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { in SelectADDRri()
104 Base = Addr.getOperand(0); in SelectADDRri()
105 Offset = Addr.getOperand(1).getOperand(0); in SelectADDRri()
121 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRrr()
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/external/llvm/lib/Target/AArch64/
DAArch64AsmPrinter.cpp34 assert(MI->getNumOperands() == 4 && MI->getOperand(0).isReg() in getDebugValueLocation()
35 && MI->getOperand(1).isImm() && "unexpected custom DBG_VALUE"); in getDebugValueLocation()
36 return MachineLocation(MI->getOperand(0).getReg(), in getDebugValueLocation()
37 MI->getOperand(1).getImm()); in getDebugValueLocation()
161 const MachineOperand &MO = MI->getOperand(OpNum); in PrintAsmOperand()
195 if (!MI->getOperand(OpNum).isImm()) in PrintAsmOperand()
197 O << MI->getOperand(OpNum).getImm(); in PrintAsmOperand()
202 return printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI, in PrintAsmOperand()
207 return printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI, in PrintAsmOperand()
225 return printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI, in PrintAsmOperand()
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/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp55 const MCOperand &MOImm = MI->getOperand(OpNum); in printOffsetSImm9Operand()
65 unsigned ExtImm = MI->getOperand(OpNum).getImm(); in printAddrRegExtendOperand()
94 const MCOperand &Imm12Op = MI->getOperand(OpNum); in printAddSubImmLSL0Operand()
118 const MCOperand &MO = MI->getOperand(OpNum); in printBareImmOperand()
125 const MCOperand &ImmROp = MI->getOperand(OpNum); in printBFILSBOperand()
133 const MCOperand &ImmSOp = MI->getOperand(OpNum); in printBFIWidthOperand()
142 const MCOperand &ImmSOp = MI->getOperand(OpNum); in printBFXWidthOperand()
143 const MCOperand &ImmROp = MI->getOperand(OpNum - 1); in printBFXWidthOperand()
156 const MCOperand &CRx = MI->getOperand(OpNum); in printCRxOperand()
165 const MCOperand &ScaleOp = MI->getOperand(OpNum); in printCVTFixedPosOperand()
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/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp88 SrcReg = MI.getOperand(1).getReg(); in isCoalescableExtInstr()
89 DstReg = MI.getOperand(0).getReg(); in isCoalescableExtInstr()
103 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && in isLoadFromStackSlot()
104 MI->getOperand(2).isFI()) { in isLoadFromStackSlot()
105 FrameIndex = MI->getOperand(2).getIndex(); in isLoadFromStackSlot()
106 return MI->getOperand(0).getReg(); in isLoadFromStackSlot()
121 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && in isStoreToStackSlot()
122 MI->getOperand(2).isFI()) { in isStoreToStackSlot()
123 FrameIndex = MI->getOperand(2).getIndex(); in isStoreToStackSlot()
124 return MI->getOperand(0).getReg(); in isStoreToStackSlot()
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/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp310 isInt32Immediate(N->getOperand(1).getNode(), Imm); in isOpcWithIntImmediate()
356 SDValue N0 = N->getOperand(0); in PreprocessISelDAG()
357 SDValue N1 = N->getOperand(1); in PreprocessISelDAG()
384 SDValue Srl = N1.getOperand(0); in PreprocessISelDAG()
406 Srl.getOperand(0), in PreprocessISelDAG()
487 BaseReg = N.getOperand(0); in SelectImmShifterOperand()
489 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1)); in SelectImmShifterOperand()
511 BaseReg = N.getOperand(0); in SelectRegShifterOperand()
513 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1)); in SelectRegShifterOperand()
516 ShReg = N.getOperand(1); in SelectRegShifterOperand()
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DARMExpandPseudoInsts.cpp78 const MachineOperand &MO = OldMI.getOperand(i); in TransferImpOps()
387 bool DstIsDead = MI.getOperand(OpIdx).isDead(); in ExpandVLD()
388 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); in ExpandVLD()
400 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
403 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
404 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
407 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
417 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
418 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
423 MachineOperand MO = MI.getOperand(SrcOpIdx); in ExpandVLD()
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/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsDirectObjLower.cpp26 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
28 int64_t Shift = Inst.getOperand(2).getImm(); in LowerLargeShift()
34 Inst.getOperand(2).setImm(Shift); in LowerLargeShift()
63 assert(InstIn.getOperand(2).isImm()); in LowerDextDins()
64 int64_t pos = InstIn.getOperand(2).getImm(); in LowerDextDins()
65 assert(InstIn.getOperand(3).isImm()); in LowerDextDins()
66 int64_t size = InstIn.getOperand(3).getImm(); in LowerDextDins()
72 InstIn.getOperand(2).setImm(pos - 32); in LowerDextDins()
78 InstIn.getOperand(3).setImm(size - 32); in LowerDextDins()

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