| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonPeephole.cpp | 234 MI->getOperand(0).setReg(PeepholeSrc); in runOnMachineFunction()
272 MI->getOperand(PR).setReg(POrig); in runOnMachineFunction()
295 Dst.setReg(Src.getReg()); in ChangeOpInto()
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| D | HexagonHardwareLoops.cpp | 970 UseMI->getOperand(0).setReg(0U); in removeIfDead()
1246 MO.setReg(NewR); in setImmediate()
1407 MO.setReg(I->first); in fixupInductionVariable()
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| /external/llvm/lib/Target/Sparc/ |
| D | FPMover.cpp | 115 MI->getOperand(0).setReg(EvenDestReg); in runOnMachineBasicBlock()
116 MI->getOperand(1).setReg(EvenSrcReg); in runOnMachineBasicBlock()
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| /external/llvm/lib/CodeGen/ |
| D | AntiDepBreaker.h | 65 MI->getOperand(0).setReg(NewReg); in UpdateDbgValue()
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| D | TargetInstrInfo.cpp | 164 MI->getOperand(0).setReg(Reg0); in commuteInstruction()
167 MI->getOperand(Idx2).setReg(Reg1); in commuteInstruction()
168 MI->getOperand(Idx1).setReg(Reg2); in commuteInstruction()
228 MO.setReg(Pred[j].getReg()); in PredicateInstruction()
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| D | TailDuplication.cpp | 435 MO.setReg(NewReg); in DuplicateInstruction()
442 MO.setReg(VI->second); in DuplicateInstruction()
508 II->getOperand(Idx).setReg(SrcReg); in UpdateSuccessorsPHIs()
520 II->getOperand(Idx).setReg(Reg); in UpdateSuccessorsPHIs()
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| D | DeadMachineInstructionElim.cpp | 139 UseMI->getOperand(0).setReg(0U); in runOnMachineFunction()
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| D | Spiller.cpp | 126 mop.setReg(newLI->reg); in trivialSpillEverywhere()
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| D | RegAllocFast.cpp | 670 MO.setReg(PhysReg); in setPhysReg()
675 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0); in setPhysReg()
858 MO.setReg(0); in AllocateBasicBlock()
879 MO.setReg(0); in AllocateBasicBlock()
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| D | MachineSSAUpdater.cpp | 230 U.setReg(NewVR); in RewriteUse()
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| D | VirtRegMap.cpp | 321 MO.setReg(PhysReg); in rewrite()
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| D | StrongPHIElimination.cpp | 722 SrcMO.setReg(CopyReg); in InsertCopiesForPHI()
770 PHI->getOperand(0).setReg(CopyReg); in InsertCopiesForPHI()
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| D | MachineRegisterInfo.cpp | 237 O.setReg(ToReg); in replaceRegWith()
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| D | TwoAddressInstructionPass.cpp | 1322 SrcMO.setReg(DstReg); in collectTiedOperands()
1418 MO.setReg(RegA); in processTiedPairs()
1435 MO.setReg(LastCopiedReg); in processTiedPairs()
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| D | PeepholeOptimizer.cpp | 292 UseMO->setReg(NewVR); in INITIALIZE_PASS_DEPENDENCY()
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| D | MachineInstr.cpp | 49 void MachineOperand::setReg(unsigned Reg) { in setReg() function in MachineOperand
74 setReg(Reg); in substVirtReg()
87 setReg(Reg); in substPhysReg()
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| /external/llvm/include/llvm/MC/ |
| D | MCInst.h | 69 void setReg(unsigned Reg) { in setReg() function
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| /external/llvm/lib/Target/R600/ |
| D | R600InstrInfo.cpp | 482 MO2.setReg(AMDGPU::PRED_SEL_ONE); in ReverseBranchCondition()
485 MO2.setReg(AMDGPU::PRED_SEL_ZERO); in ReverseBranchCondition()
514 PMO.setReg(Pred[2].getReg()); in PredicateInstruction()
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| D | AMDILCFGStructurizer.cpp | 1531 RegiT setReg) { in mergeLoopbreakBlock() argument
1556 if (exitBlk == exitLandBlk && setReg == INVALIDREGNUM) { in mergeLoopbreakBlock()
1573 if (setReg != INVALIDREGNUM) { in mergeLoopbreakBlock()
1574 CFGTraits::insertAssignInstrBefore(branchInstrPos, passRep, setReg, 1); in mergeLoopbreakBlock()
1595 RegiT setReg) { in settleLoopcontBlock() argument
1622 (setReg == INVALIDREGNUM && (&*contingBlk->rbegin()) == branchInstr); in settleLoopcontBlock()
1631 if (setReg != INVALIDREGNUM) { in settleLoopcontBlock()
1632 CFGTraits::insertAssignInstrBefore(branchInstrPos, passRep, setReg, 1); in settleLoopcontBlock()
1654 if (setReg != INVALIDREGNUM) { in settleLoopcontBlock()
1655 CFGTraits::insertAssignInstrBefore(contingBlk, passRep, setReg, 1); in settleLoopcontBlock()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 186 MI->getOperand(0).setReg(Reg2); in commuteInstruction()
187 MI->getOperand(2).setReg(Reg1); in commuteInstruction()
188 MI->getOperand(1).setReg(Reg2); in commuteInstruction()
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| D | PPCCTRLoops.cpp | 162 void setReg(unsigned Val) { in setReg() function in __anon9f6c02960111::CountValue
586 UseMI->getOperand(0).setReg(0U); in removeIfDead()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineOperand.h | 337 void setReg(unsigned Reg);
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| D | ScheduleDAG.h | 253 void setReg(unsigned Reg) { in setReg() function
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 233 MI->getOperand(OpNo).setReg(getX86SubSuperRegister(Reg, MVT::i32)); in lower_subreg32()
245 MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64)); in lower_lea64_32mem()
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| D | X86FloatingPoint.cpp | 1273 MI->getOperand(0).setReg(getSTReg(Op1)); in handleCompareFP()
1300 MI->getOperand(0).setReg(getSTReg(Op1)); in handleCondMovFP()
1601 Op.setReg(getSTReg(FPReg)); in handleSpecialFP()
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