| /external/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.h | 80 v16i16 = 29, // 16 x i16 enumerator
219 SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 || in is256BitVector()
278 case v16i16: in getVectorElementType()
312 case v16i16: in getVectorNumElements()
394 case v16i16: in getSizeInBits()
503 if (NumElements == 16) return MVT::v16i16; in getVectorVT()
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| D | ValueTypes.td | 52 def v16i16 : ValueType<256, 29>; // 16 x i16 vector value
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| /external/llvm/test/CodeGen/X86/ |
| D | avx2-cmp.ll | 18 define <16 x i16> @v16i16-cmp(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
46 define <16 x i16> @v16i16-cmpeq(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
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| D | avx-cmp.ll | 72 define <16 x i16> @v16i16-cmp(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
116 define <16 x i16> @v16i16-cmpeq(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
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| D | pmovsx-inreg.ll | 89 ; FIXME: v16i8 -> v16i16 is scalarized.
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| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 242 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
243 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
269 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost()
270 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 } in getCastInstrCost()
392 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 2*16 + 1 + 3*1 + 4*1 }, in getCmpSelInstrCost()
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86InstComments.cpp | 119 DecodePSHUFHWMask(MVT::v16i16, in EmitAnyX86InstComments()
139 DecodePSHUFLWMask(MVT::v16i16, in EmitAnyX86InstComments()
178 DecodeUNPCKHMask(MVT::v16i16, ShuffleMask); in EmitAnyX86InstComments()
251 DecodeUNPCKLMask(MVT::v16i16, ShuffleMask); in EmitAnyX86InstComments()
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| /external/llvm/lib/Target/X86/ |
| D | X86CallingConv.td | 49 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
210 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
227 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
247 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
342 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
350 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
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| D | X86TargetTransformInfo.cpp | 301 { ISD::SETCC, MVT::v16i16, 4 }, in getCmpSelInstrCost()
308 { ISD::SETCC, MVT::v16i16, 1 }, in getCmpSelInstrCost()
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| D | X86InstrSSE.td | 261 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
262 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
278 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
335 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
341 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
346 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
351 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
353 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
357 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
358 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
[all …]
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| D | X86ISelLowering.cpp | 1079 addRegisterClass(MVT::v16i16, &X86::VR256RegClass); in X86TargetLowering()
1130 setOperationAction(ISD::SRL, MVT::v16i16, Custom); in X86TargetLowering()
1133 setOperationAction(ISD::SHL, MVT::v16i16, Custom); in X86TargetLowering()
1136 setOperationAction(ISD::SRA, MVT::v16i16, Custom); in X86TargetLowering()
1139 setOperationAction(ISD::SDIV, MVT::v16i16, Custom); in X86TargetLowering()
1142 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); in X86TargetLowering()
1174 setOperationAction(ISD::ADD, MVT::v16i16, Legal); in X86TargetLowering()
1179 setOperationAction(ISD::SUB, MVT::v16i16, Legal); in X86TargetLowering()
1184 setOperationAction(ISD::MUL, MVT::v16i16, Legal); in X86TargetLowering()
1201 setOperationAction(ISD::ADD, MVT::v16i16, Custom); in X86TargetLowering()
[all …]
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| D | X86InstrFragmentsSIMD.td | 383 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
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| D | X86RegisterInfo.td | 412 def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 147 case MVT::v16i16: return "v16i16"; in getEVTString()
210 case MVT::v16i16: return VectorType::get(Type::getInt16Ty(Context), 16); in getTypeForEVT()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 88 case MVT::v16i16: return "MVT::v16i16"; in getEnumName()
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 142 def llvm_v16i16_ty : LLVMType<v16i16>; // 16 x i16
|