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Searched refs:LHSKnownZero (Results 1 – 5 of 5) sorted by relevance

/external/llvm/lib/Transforms/InstCombine/
DInstCombineSimplifyDemanded.cpp141 APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0); in SimplifyDemandedUseBits() local
161 ComputeMaskedBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1); in SimplifyDemandedUseBits()
166 if ((DemandedMask & ~LHSKnownZero & RHSKnownOne) == in SimplifyDemandedUseBits()
167 (DemandedMask & ~LHSKnownZero)) in SimplifyDemandedUseBits()
174 if ((DemandedMask & (RHSKnownZero|LHSKnownZero)) == DemandedMask) in SimplifyDemandedUseBits()
183 ComputeMaskedBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1); in SimplifyDemandedUseBits()
191 if ((DemandedMask & ~RHSKnownOne & LHSKnownZero) == in SimplifyDemandedUseBits()
200 if ((DemandedMask & (~LHSKnownZero) & RHSKnownOne) == in SimplifyDemandedUseBits()
201 (DemandedMask & (~LHSKnownZero))) in SimplifyDemandedUseBits()
208 ComputeMaskedBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1); in SimplifyDemandedUseBits()
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DInstCombineAddSub.cpp936 APInt LHSKnownZero(IT->getBitWidth(), 0); in visitAdd() local
937 ComputeMaskedBits(XorLHS, LHSKnownZero, LHSKnownOne); in visitAdd()
938 if ((XorRHS->getValue() | LHSKnownZero).isAllOnesValue()) in visitAdd()
997 APInt LHSKnownZero(IT->getBitWidth(), 0); in visitAdd() local
998 ComputeMaskedBits(LHS, LHSKnownZero, LHSKnownOne); in visitAdd()
999 if (LHSKnownZero != 0) { in visitAdd()
1005 if ((LHSKnownZero|RHSKnownZero).isAllOnesValue()) in visitAdd()
DInstCombineCalls.cpp354 APInt LHSKnownZero(BitWidth, 0); in visitCallInst() local
356 ComputeMaskedBits(LHS, LHSKnownZero, LHSKnownOne); in visitCallInst()
358 bool LHSKnownPositive = LHSKnownZero[BitWidth - 1]; in visitCallInst()
448 APInt LHSKnownZero(BitWidth, 0); in visitCallInst() local
450 ComputeMaskedBits(LHS, LHSKnownZero, LHSKnownOne); in visitCallInst()
456 APInt LHSMax = ~LHSKnownZero; in visitCallInst()
/external/llvm/lib/Analysis/
DValueTracking.cpp80 APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0); in ComputeMaskedBitsAddSub() local
81 llvm::ComputeMaskedBits(Op0, LHSKnownZero, LHSKnownOne, TD, Depth+1); in ComputeMaskedBitsAddSub()
82 assert((LHSKnownZero & LHSKnownOne) == 0 && in ComputeMaskedBitsAddSub()
84 unsigned LHSKnownZeroOut = LHSKnownZero.countTrailingOnes(); in ComputeMaskedBitsAddSub()
106 KnownZero |= LHSKnownZero & Mask; in ComputeMaskedBitsAddSub()
115 if (LHSKnownZero.isNegative() && KnownZero2.isNegative()) in ComputeMaskedBitsAddSub()
122 if (LHSKnownZero.isNegative() && KnownOne2.isNegative()) in ComputeMaskedBitsAddSub()
574 APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0); in ComputeMaskedBits() local
575 ComputeMaskedBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, TD, in ComputeMaskedBits()
578 if (LHSKnownZero.isNegative()) in ComputeMaskedBits()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp954 APInt LHSKnownZero, LHSKnownOne; in SelectAddressRegReg() local
957 LHSKnownZero, LHSKnownOne); in SelectAddressRegReg()
959 if (LHSKnownZero.getBoolValue()) { in SelectAddressRegReg()
964 if (~(LHSKnownZero | RHSKnownZero) == 0) { in SelectAddressRegReg()
1015 APInt LHSKnownZero, LHSKnownOne; in SelectAddressRegImm() local
1016 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne); in SelectAddressRegImm()
1018 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { in SelectAddressRegImm()
1128 APInt LHSKnownZero, LHSKnownOne; in SelectAddressRegImmShift() local
1129 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne); in SelectAddressRegImmShift()
1130 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { in SelectAddressRegImmShift()