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Searched refs:CopyFromReg (Results 1 – 17 of 17) sorted by relevance

/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp89 case ISD::CopyFromReg: NumberDeps++; break; in numberRCValPredInSU()
126 case ISD::CopyFromReg: break; in numberRCValSuccInSU()
458 case ISD::CopyFromReg: in SUSchedulingCost()
564 case ISD::CopyFromReg: in initNumRegDefsLeft()
DInstrEmitter.cpp336 Op.getNode()->getOpcode() != ISD::CopyFromReg && in AddRegisterOperand()
800 if (F->getOpcode() == ISD::CopyFromReg) { in EmitMachineNode()
865 case ISD::CopyFromReg: { in EmitSpecialNode()
DScheduleDAGRRList.cpp288 if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) { in GetCostForDef()
681 case ISD::CopyFromReg: in EmitNode()
2136 if (PN->getOpcode() == ISD::CopyFromReg) { in unscheduledNode()
2230 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) { in hasOnlyLiveInOpers()
2304 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg && in resetVRegCycle()
2322 I->getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) { in hasVRegCycleUse()
2854 if (N->getOpcode() == ISD::CopyFromReg && in PrescheduleNodesWithMultipleUses()
DSelectionDAGDumper.cpp126 case ISD::CopyFromReg: return "CopyFromReg"; in getOperationName()
DScheduleDAGSDNodes.cpp532 if (Node->getOpcode() == ISD::CopyFromReg) in InitNodeNumDefs()
DSelectionDAGISel.cpp1753 UserOpcode == ISD::CopyFromReg || in WalkChainUsers()
2169 case ISD::CopyFromReg: in SelectCodeCommon()
DSelectionDAGBuilder.cpp4363 if (CFR.getOpcode() == ISD::CopyFromReg) in getTruncatedArgReg()
4397 if (N.getOpcode() == ISD::CopyFromReg) in EmitFuncArgumentDbgValue()
6618 assert((Op.getOpcode() != ISD::CopyFromReg || in CopyValueToVirtualRegister()
6840 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { in LowerArguments()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h151 CopyFromReg, enumerator
DSelectionDAG.h467 return getNode(ISD::CopyFromReg, dl, VTs, Ops, 2);
477 return getNode(ISD::CopyFromReg, dl, VTs, Ops, Glue.getNode() ? 3 : 2);
/external/llvm/lib/Target/X86/
DREADME-X86-64.txt46 emits a CopyFromReg which gets turned into a movb and that can be allocated a
49 To get around this, isel emits a CopyFromReg from AX and then right shift it
DX86InstrCompiler.td1144 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1151 N->getOpcode() != ISD::CopyFromReg &&
DX86ISelDAGToDAG.cpp1150 RHS.getNode()->getOpcode() == ISD::CopyFromReg || in MatchAddressRecursively()
DX86ISelLowering.cpp2970 if (Arg.getOpcode() == ISD::CopyFromReg) { in MatchingStackOffset()
10138 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){ in LowerSELECT()
/external/llvm/lib/Target/R600/
DSIISelLowering.cpp684 case ISD::CopyFromReg: { in getRegClassForNode()
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td294 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
300 N->getOpcode() != ISD::CopyFromReg;
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1149 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) in LowerCall_64()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp1876 if (Arg.getOpcode() == ISD::CopyFromReg) { in MatchingStackOffset()