| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFormats.td | 61 field bits<32> Inst;
71 let Inst{31-26} = Opcode;
142 let Inst{25-21} = rs;
143 let Inst{20-16} = rt;
144 let Inst{15-11} = rd;
145 let Inst{10-6} = shamt;
146 let Inst{5-0} = funct;
162 let Inst{25-21} = rs;
163 let Inst{20-16} = rt;
164 let Inst{15-0} = imm16;
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| D | MipsDSPInstrFormats.td | 41 let Inst{25-21} = rs;
42 let Inst{20-16} = rt;
43 let Inst{15-11} = rd;
44 let Inst{10-6} = op;
45 let Inst{5-0} = 0b010000;
54 let Inst{25-21} = rs;
55 let Inst{20-16} = 0;
56 let Inst{15-11} = rd;
57 let Inst{10-6} = op;
58 let Inst{5-0} = 0b010000;
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| D | MicroMipsInstrFormats.td | 11 bits<32> Inst;
13 let Inst{31-26} = op;
14 let Inst{25-21} = rt;
15 let Inst{20-16} = rs;
16 let Inst{15-11} = rd;
17 let Inst{10} = 0;
18 let Inst{9-0} = funct;
26 bits<32> Inst;
28 let Inst{31-26} = op;
29 let Inst{25-21} = rt;
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| D | Mips16InstrFormats.td | 59 field bits<16> Inst;
63 let Inst{15-11} = Opcode;
76 field bits<32> Inst;
86 let Inst{31-27} = 0b11110;
111 let Inst{10-0} = imm11;
127 let Inst{10-8} = rx;
128 let Inst{7-0} = imm8;
146 let Inst{10-8} = rx;
147 let Inst{7-5} = ry;
148 let Inst{4-0} = funct;
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| /external/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 87 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
92 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
97 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
100 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
103 static DecodeStatus Decode2RInstruction(MCInst &Inst,
108 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
113 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
118 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
123 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
128 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
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| /external/llvm/lib/Target/R600/ |
| D | SIInstrFormats.td | 29 field bits<32> Inst;
36 field bits<64> Inst;
50 let Inst{7-0} = SSRC0;
51 let Inst{15-8} = op;
52 let Inst{22-16} = SDST;
53 let Inst{31-23} = 0x17d; //encoding;
67 let Inst{7-0} = SSRC0;
68 let Inst{15-8} = SSRC1;
69 let Inst{22-16} = SDST;
70 let Inst{29-23} = op;
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| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 50 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, in decodeRegisterClass() argument
59 Inst.addOperand(MCOperand::CreateReg(RegNo)); in decodeRegisterClass()
63 static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGR32BitRegisterClass() argument
66 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs); in DecodeGR32BitRegisterClass()
69 static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGR64BitRegisterClass() argument
72 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs); in DecodeGR64BitRegisterClass()
75 static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGR128BitRegisterClass() argument
78 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs); in DecodeGR128BitRegisterClass()
81 static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeADDR64BitRegisterClass() argument
84 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, true); in DecodeADDR64BitRegisterClass()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 25 field bits<32> Inst;
76 let Inst{4-0} = Rd;
84 let Inst{4-0} = Rt;
94 let Inst{9-5} = Rn;
103 let Inst{9-5} = Rn;
112 let Inst{14-10} = Rt2;
120 let Inst{20-16} = Rm;
135 let Inst{31} = sf;
136 let Inst{30} = op;
137 let Inst{29} = S;
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 65 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
68 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
71 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
74 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
77 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
79 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
81 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
83 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
85 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
88 static DecodeStatus DecodeVPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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| /external/llvm/lib/Transforms/Scalar/ |
| D | EarlyCSE.cpp | 50 Instruction *Inst; member
52 SimpleValue(Instruction *I) : Inst(I) { in SimpleValue()
57 return Inst == DenseMapInfo<Instruction*>::getEmptyKey() || in isSentinel()
58 Inst == DenseMapInfo<Instruction*>::getTombstoneKey(); in isSentinel()
61 static bool canHandle(Instruction *Inst) { in canHandle()
63 if (CallInst *CI = dyn_cast<CallInst>(Inst)) in canHandle()
65 return isa<CastInst>(Inst) || isa<BinaryOperator>(Inst) || in canHandle()
66 isa<GetElementPtrInst>(Inst) || isa<CmpInst>(Inst) || in canHandle()
67 isa<SelectInst>(Inst) || isa<ExtractElementInst>(Inst) || in canHandle()
68 isa<InsertElementInst>(Inst) || isa<ShuffleVectorInst>(Inst) || in canHandle()
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| D | Sink.cpp | 58 bool AllUsesDominatedByBlock(Instruction *Inst, BasicBlock *BB) const;
59 bool IsAcceptableTarget(Instruction *Inst, BasicBlock *SuccToSinkTo) const;
74 bool Sinking::AllUsesDominatedByBlock(Instruction *Inst, in AllUsesDominatedByBlock() argument
80 for (Value::use_iterator I = Inst->use_begin(), in AllUsesDominatedByBlock()
81 E = Inst->use_end(); I != E; ++I) { in AllUsesDominatedByBlock()
136 Instruction *Inst = I; // The instruction to sink. in ProcessBlock() local
144 if (isa<DbgInfoIntrinsic>(Inst)) in ProcessBlock()
147 if (SinkInstruction(Inst, Stores)) in ProcessBlock()
156 static bool isSafeToMove(Instruction *Inst, AliasAnalysis *AA, in isSafeToMove() argument
159 if (Inst->mayWriteToMemory()) { in isSafeToMove()
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
159 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
162 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
164 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
166 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
168 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
170 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
172 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
174 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIInstrInfo.td | 45 field bits<32> Inst;
51 field bits<64> Inst;
129 let Inst{3-0} = EN;
130 let Inst{9-4} = TGT;
131 let Inst{10} = COMPR;
132 let Inst{11} = DONE;
133 let Inst{12} = VM;
134 let Inst{31-26} = 0x3e;
135 let Inst{39-32} = VSRC0;
136 let Inst{47-40} = VSRC1;
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | SIInstrInfo.td | 45 field bits<32> Inst;
51 field bits<64> Inst;
129 let Inst{3-0} = EN;
130 let Inst{9-4} = TGT;
131 let Inst{10} = COMPR;
132 let Inst{11} = DONE;
133 let Inst{12} = VM;
134 let Inst{31-26} = 0x3e;
135 let Inst{39-32} = VSRC0;
136 let Inst{47-40} = VSRC1;
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrFormats.td | 16 field bits<32> Inst;
21 let Inst{0-5} = opcode;
69 field bits<64> Inst;
74 let Inst{0-5} = opcode1;
75 let Inst{32-37} = opcode2;
105 let Inst{6-29} = LI;
106 let Inst{30} = aa;
107 let Inst{31} = lk;
121 let Inst{6-10} = BIBO{4-0};
122 let Inst{11-15} = BI;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrFormats.td | 292 field bits<32> Inst;
295 // target encoding differs from its value in the "Inst" field,
402 let Inst{31-28} = p;
434 let Inst{31-28} = p;
435 let Inst{20} = s;
478 let Inst{27-24} = opcod;
484 let Inst{27-24} = opcod;
500 let Inst{27-23} = 0b00011;
501 let Inst{22-21} = opcod;
502 let Inst{20} = 1;
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| D | ARMInstrThumb2.td | 299 let Inst{11-8} = Rd;
300 let Inst{26} = imm{11};
301 let Inst{14-12} = imm{10-8};
302 let Inst{7-0} = imm{7-0};
313 let Inst{11-8} = Rd;
314 let Inst{26} = imm{11};
315 let Inst{14-12} = imm{10-8};
316 let Inst{7-0} = imm{7-0};
325 let Inst{19-16} = Rn;
326 let Inst{26} = imm{11};
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 222 void cvtThumbMultiply(MCInst &Inst,
224 bool validateInstruction(MCInst &Inst,
226 bool processInstruction(MCInst &Inst,
232 bool isDeprecated(MCInst &Inst, StringRef &Info);
274 unsigned checkTargetMatchPredicate(MCInst &Inst);
1485 void addExpr(MCInst &Inst, const MCExpr *Expr) const { in addExpr() argument
1488 Inst.addOperand(MCOperand::CreateImm(0)); in addExpr()
1490 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); in addExpr()
1492 Inst.addOperand(MCOperand::CreateExpr(Expr)); in addExpr()
1495 void addCondCodeOperands(MCInst &Inst, unsigned N) const { in addCondCodeOperands() argument
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| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 91 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
96 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
101 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
106 static DecodeStatus DecodeDSPRegsRegisterClass(MCInst &Inst,
111 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
116 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
121 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
126 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
131 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
136 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
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| /external/llvm/utils/TableGen/ |
| D | InstrInfoEmitter.cpp | 55 void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
70 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
87 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { in GetOperandInfo() argument
90 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) { in GetOperandInfo()
99 DagInit *MIOI = Inst.Operands[i].MIOperandInfo; in GetOperandInfo()
103 OperandList.push_back(Inst.Operands[i]); in GetOperandInfo()
105 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) { in GetOperandInfo()
106 OperandList.push_back(Inst.Operands[i]); in GetOperandInfo()
136 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand")) in GetOperandInfo()
141 if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand")) in GetOperandInfo()
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrAnalysis.h | 31 virtual bool isBranch(const MCInst &Inst) const { in isBranch() argument
32 return Info->get(Inst.getOpcode()).isBranch(); in isBranch()
35 virtual bool isConditionalBranch(const MCInst &Inst) const { in isConditionalBranch() argument
36 return Info->get(Inst.getOpcode()).isConditionalBranch(); in isConditionalBranch()
39 virtual bool isUnconditionalBranch(const MCInst &Inst) const { in isUnconditionalBranch() argument
40 return Info->get(Inst.getOpcode()).isUnconditionalBranch(); in isUnconditionalBranch()
43 virtual bool isIndirectBranch(const MCInst &Inst) const { in isIndirectBranch() argument
44 return Info->get(Inst.getOpcode()).isIndirectBranch(); in isIndirectBranch()
47 virtual bool isCall(const MCInst &Inst) const { in isCall() argument
48 return Info->get(Inst.getOpcode()).isCall(); in isCall()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrFormats.td | 15 field bits<32> Inst;
38 let Inst{15-11} = opc;
52 let Inst{31-27} = opc{8-4};
53 let Inst{26-20} = 0b1111110;
54 let Inst{19-16} = opc{3-0};
56 let Inst{15-11} = 0b11111;
68 let Inst{15-11} = opc;
81 let Inst{31-27} = opc{8-4};
82 let Inst{26-20} = 0b1111110;
83 let Inst{19-16} = opc{3-0};
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| /external/llvm/lib/Analysis/ |
| D | PHITransAddr.cpp | 25 static bool CanPHITrans(Instruction *Inst) { in CanPHITrans() argument
26 if (isa<PHINode>(Inst) || in CanPHITrans()
27 isa<GetElementPtrInst>(Inst)) in CanPHITrans()
30 if (isa<CastInst>(Inst) && in CanPHITrans()
31 isSafeToSpeculativelyExecute(Inst)) in CanPHITrans()
34 if (Inst->getOpcode() == Instruction::Add && in CanPHITrans()
35 isa<ConstantInt>(Inst->getOperand(1))) in CanPHITrans()
118 Instruction *Inst = dyn_cast<Instruction>(Addr); in IsPotentiallyPHITranslatable() local
119 return Inst == 0 || CanPHITrans(Inst); in IsPotentiallyPHITranslatable()
149 Instruction *Inst = dyn_cast<Instruction>(V); in PHITranslateSubExpr() local
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| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 208 void ProcessInstruction(MCInst &Inst,
385 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands()
389 void addRegGPRCOperands(MCInst &Inst, unsigned N) const { in addRegGPRCOperands()
391 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()])); in addRegGPRCOperands()
394 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const { in addRegGPRCNoR0Operands()
396 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()])); in addRegGPRCNoR0Operands()
399 void addRegG8RCOperands(MCInst &Inst, unsigned N) const { in addRegG8RCOperands()
401 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()])); in addRegG8RCOperands()
404 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const { in addRegG8RCNoX0Operands()
406 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()])); in addRegG8RCNoX0Operands()
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| /external/llvm/lib/Transforms/ObjCARC/ |
| D | DependencyAnalysis.cpp | 35 llvm::objcarc::CanAlterRefCount(const Instruction *Inst, const Value *Ptr, in CanAlterRefCount() argument
48 ImmutableCallSite CS = static_cast<const Value *>(Inst); in CanAlterRefCount()
72 llvm::objcarc::CanUse(const Instruction *Inst, const Value *Ptr, in CanUse() argument
80 if (const ICmpInst *ICI = dyn_cast<ICmpInst>(Inst)) { in CanUse()
86 } else if (ImmutableCallSite CS = static_cast<const Value *>(Inst)) { in CanUse()
95 } else if (const StoreInst *SI = dyn_cast<StoreInst>(Inst)) { in CanUse()
105 for (User::const_op_iterator OI = Inst->op_begin(), OE = Inst->op_end(); in CanUse()
117 llvm::objcarc::Depends(DependenceKind Flavor, Instruction *Inst, in Depends() argument
120 if (Inst == Arg) in Depends()
125 InstructionClass Class = GetInstructionClass(Inst); in Depends()
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