| /external/llvm/lib/Target/X86/ |
| D | X86InstrControl.td | 115 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
122 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
222 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst),
285 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst),
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| D | X86InstrShiftRotate.td | 72 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
75 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
79 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
82 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
86 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
90 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
95 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
99 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
105 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
109 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
[all …]
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| D | X86InstrSystem.td | 357 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
421 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
449 def XSAVE : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
451 def XSAVE64 : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
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| D | X86CodeEmitter.cpp | 221 case X86II::MRM4m: case X86II::MRM5m: in determineREX()
1003 case X86II::MRM4m: case X86II::MRM5m: in emitVEXOpcodePrefix()
1389 case X86II::MRM4m: case X86II::MRM5m: in emitInstruction()
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| D | X86InstrFPStack.td | 214 defm SUB : FPBinary<fsub, MRM4m, "sub">;
284 def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">;
293 def FRSTORm : FPI<0xDD, MRM4m, (outs f32mem:$dst), (ins), "frstor\t$dst">;
300 def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f32mem:$src), "fbld\t$src">;
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| D | X86InstrArithmetic.td | 86 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
96 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
101 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
106 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
1192 defm AND : ArithBinOp_RF<0x20, 0x22, 0x24, "and", MRM4r, MRM4m,
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| D | X86InstrInfo.td | 1262 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1266 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1270 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
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| D | X86InstrFormats.td | 29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
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| D | X86InstrCompiler.td | 689 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 269 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 enumerator
634 case X86II::MRM4m: case X86II::MRM5m: in getMemoryOperandNo()
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| D | X86MCCodeEmitter.cpp | 780 case X86II::MRM4m: case X86II::MRM5m: in EmitVEXOpcodePrefix()
1005 case X86II::MRM4m: case X86II::MRM5m: in DetermineREXPrefix()
1354 case X86II::MRM4m: case X86II::MRM5m: in EncodeInstruction()
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| /external/llvm/utils/TableGen/ |
| D | X86RecognizableInstr.cpp | 65 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, enumerator
840 case X86Local::MRM4m: in emitInstructionSpecifier()
938 case X86Local::MRM4m: in emitDecodePath()
981 case X86Local::MRM4m: in emitDecodePath()
1062 case X86Local::MRM4m: in emitDecodePath()
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| /external/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 56 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
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| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 1766 case X86II::MRM4m: case X86II::MRM5m: // use the Mod/RM byte and a field
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