| /external/llvm/lib/Target/X86/ |
| D | X86InstrVMX.td | 34 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
42 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
64 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
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| D | X86CodeEmitter.cpp | 222 case X86II::MRM6m: case X86II::MRM7m: in determineREX()
1004 case X86II::MRM6m: case X86II::MRM7m: { in emitVEXOpcodePrefix()
1390 case X86II::MRM6m: case X86II::MRM7m: { in emitInstruction()
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| D | X86InstrFPStack.td | 217 defm DIV : FPBinary<fdiv, MRM6m, "div">;
285 def FSTENVm : FPI<0xD9, MRM6m, (outs f32mem:$dst), (ins), "fnstenv\t$dst">;
294 def FSAVEm : FPI<0xDD, MRM6m, (outs f32mem:$dst), (ins), "fnsave\t$dst">;
301 def FBSTPm : FPI<0xDF, MRM6m, (outs f32mem:$dst), (ins), "fbstp\t$dst">;
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| D | X86InstrSystem.td | 426 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
457 def XSAVEOPT : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
459 def XSAVEOPT64 : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
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| D | X86InstrArithmetic.td | 314 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
318 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
322 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
327 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
1196 defm XOR : ArithBinOp_RF<0x30, 0x32, 0x34, "xor", MRM6r, MRM6m,
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| D | X86InstrInfo.td | 860 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
865 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
897 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
1348 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1351 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1353 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
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| D | X86InstrFormats.td | 30 def MRM6m : Format<30>; def MRM7m : Format<31>;
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| D | X86InstrCompiler.td | 690 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
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| /external/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 57 def MRM6m : Format<30>; def MRM7m : Format<31>;
116 "xor $dst, $src2", 0x81, MRM6m,
127 "xor $dst, $src2", 0x81, MRM6m,
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 269 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 enumerator
635 case X86II::MRM6m: case X86II::MRM7m: { in getMemoryOperandNo()
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| D | X86MCCodeEmitter.cpp | 781 case X86II::MRM6m: case X86II::MRM7m: { in EmitVEXOpcodePrefix()
1006 case X86II::MRM6m: case X86II::MRM7m: in DetermineREXPrefix()
1355 case X86II::MRM6m: case X86II::MRM7m: in EncodeInstruction()
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| /external/llvm/utils/TableGen/ |
| D | X86RecognizableInstr.cpp | 65 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, enumerator
842 case X86Local::MRM6m: in emitInstructionSpecifier()
940 case X86Local::MRM6m: in emitDecodePath()
983 case X86Local::MRM6m: in emitDecodePath()
1064 case X86Local::MRM6m: in emitDecodePath()
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| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 1767 case X86II::MRM6m: case X86II::MRM7m: // to hold extended opcode data
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