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Searched refs:MRMDestReg (Results 1 – 16 of 16) sorted by relevance

/external/llvm/test/TableGen/
DTargetInstrInfo.td49 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
88 "mov $dst, $src", 0x88, MRMDestReg,
102 "and $dst, $src2", 0x20, MRMDestReg,
/external/llvm/lib/Target/X86/
DX86InstrVMX.td48 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
52 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
DX86InstrInfo.td1031 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1033 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1035 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1037 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1172 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1205 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1209 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1212 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1278 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1281 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
[all …]
DX86InstrSystem.td127 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
129 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
142 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
144 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
169 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
171 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
173 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
DX86InstrShiftRotate.td700 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
706 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
712 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
717 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
722 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
728 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
737 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
744 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
751 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
758 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
[all …]
DX86InstrAVX512.td210 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
220 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
233 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
243 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
338 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
466 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
DX86InstrSSE.td476 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
858 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
862 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
866 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
870 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
874 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
878 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
882 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
886 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
934 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
[all …]
DX86InstrMMX.td233 def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src),
248 def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
DX86CodeEmitter.cpp1041 case X86II::MRMDestReg: in emitVEXOpcodePrefix()
1286 case X86II::MRMDestReg: { in emitInstruction()
DX86InstrArithmetic.td689 Format f = MRMDestReg>
707 SDPatternOperator opnode, Format f = MRMDestReg>
DX86InstrFormats.td22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h241 MRMDestReg = 3, enumerator
603 case X86II::MRMDestReg: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp839 case X86II::MRMDestReg: in EmitVEXOpcodePrefix()
1262 case X86II::MRMDestReg: in EncodeInstruction()
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp58 MRMDestReg = 3, enumerator
148 if (form == X86Local::MRMDestReg || in needsModRMForDecode()
166 if (form == X86Local::MRMDestReg || in isRegFormat()
695 case X86Local::MRMDestReg: in emitInstructionSpecifier()
/external/llvm/docs/
DTableGenFundamentals.rst108 Format Form = MRMDestReg;
142 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
DWritingAnLLVMBackend.rst1746 case X86II::MRMDestReg:// for instructions that use the Mod/RM byte