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Searched refs:MRMSrcReg (Results 1 – 20 of 20) sorted by relevance

/external/llvm/lib/Target/X86/
DX86InstrMMX.td93 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
111 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
133 def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
150 def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst),
167 def R64irr : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
181 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
192 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
214 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
240 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
253 def MMX_MOVD64rrv164 : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
[all …]
DX86InstrExtension.td43 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
51 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src),
59 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
69 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
77 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
85 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
98 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
113 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
121 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
129 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
[all …]
DX86InstrXOP.td15 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
44 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
61 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
76 def rrY : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
92 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
126 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
146 def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
178 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
206 def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
236 def rrY : IXOPi8<opc, MRMSrcReg, (outs VR256:$dst),
[all …]
DX86Instr3DNow.td37 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, []>;
42 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
52 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src1), Mn, []>;
57 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn,
DX86InstrFMA.td24 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
40 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
122 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
142 def r_Int : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
204 def rr : FMA4<opc, MRMSrcReg, (outs RC:$dst),
224 def rr_REV : FMA4<opc, MRMSrcReg, (outs RC:$dst),
233 def rr_Int : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
257 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
277 def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
298 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
[all …]
DX86InstrSSE.td164 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
185 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
209 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
231 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
467 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
773 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1080 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1083 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1086 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1089 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
[all …]
DX86InstrAVX512.td88 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
101 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
113 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
127 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
193 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
356 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
381 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
384 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
410 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
414 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
[all …]
DX86InstrSystem.td132 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
134 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
147 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
149 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
183 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
185 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
187 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
206 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
212 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
217 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
[all …]
DX86InstrCMovSetCC.td21 : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
27 : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
33 :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
DX86InstrVMX.td56 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
60 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
DX86InstrArithmetic.td156 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
161 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
166 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
206 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
212 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
219 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
225 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
231 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
237 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
733 : ITy<opcode, MRMSrcReg, typeinfo,
[all …]
DX86InstrInfo.td944 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
952 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
960 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
969 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
978 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
986 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1127 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1129 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1131 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1133 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
[all …]
DX86CodeEmitter.cpp193 case X86II::MRMSrcReg: { in determineREX()
1019 case X86II::MRMSrcReg: in emitVEXOpcodePrefix()
1310 case X86II::MRMSrcReg: { in emitInstruction()
DX86InstrShiftRotate.td872 def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, i8imm:$src2),
885 def rr : I<0xF7, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
DX86InstrFormats.td23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h251 MRMSrcReg = 5, enumerator
604 case X86II::MRMSrcReg: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp803 case X86II::MRMSrcReg: in EmitVEXOpcodePrefix()
976 case X86II::MRMSrcReg: in DetermineREXPrefix()
1293 case X86II::MRMSrcReg: in EncodeInstruction()
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp60 MRMSrcReg = 5, enumerator
150 form == X86Local::MRMSrcReg || in needsModRMForDecode()
167 form == X86Local::MRMSrcReg || in isRegFormat()
741 case X86Local::MRMSrcReg: in emitInstructionSpecifier()
/external/llvm/test/TableGen/
DTargetInstrInfo.td50 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
/external/llvm/docs/
DWritingAnLLVMBackend.rst1752 case X86II::MRMSrcReg: // for instructions that use the Mod/RM byte