| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 50 unsigned Opc = MI->getOpcode(); in isLoadFromStackSlot() local
52 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) || in isLoadFromStackSlot()
53 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) || in isLoadFromStackSlot()
54 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) || in isLoadFromStackSlot()
55 (Opc == Mips::LDC164_P8)) { in isLoadFromStackSlot()
75 unsigned Opc = MI->getOpcode(); in isStoreToStackSlot() local
77 if ((Opc == Mips::SW) || (Opc == Mips::SW_P8) || (Opc == Mips::SD) || in isStoreToStackSlot()
78 (Opc == Mips::SD_P8) || (Opc == Mips::SWC1) || (Opc == Mips::SWC1_P8) || in isStoreToStackSlot()
79 (Opc == Mips::SDC1) || (Opc == Mips::SDC164) || in isStoreToStackSlot()
80 (Opc == Mips::SDC164_P8)) { in isStoreToStackSlot()
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| D | Mips16InstrInfo.cpp | 72 unsigned Opc = 0; in copyPhysReg() local
76 Opc = Mips::MoveR3216; in copyPhysReg()
79 Opc = Mips::Move32R16; in copyPhysReg()
82 Opc = Mips::Mfhi16, SrcReg = 0; in copyPhysReg()
86 Opc = Mips::Mflo16, SrcReg = 0; in copyPhysReg()
89 assert(Opc && "Cannot copy registers"); in copyPhysReg()
91 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg()
108 unsigned Opc = 0; in storeRegToStack() local
110 Opc = Mips::SwRxSpImmX16; in storeRegToStack()
111 assert(Opc && "Register class not handled!"); in storeRegToStack()
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| D | MipsSEInstrInfo.h | 68 virtual unsigned getOppositeBranchOpc(unsigned Opc) const;
82 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const;
85 unsigned Opc) const;
87 std::pair<bool, bool> compareOpndSize(unsigned Opc,
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| D | Mips16ISelDAGToDAG.cpp | 45 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, SDLoc DL, EVT Ty, in selectMULT() argument
48 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0), in selectMULT()
255 unsigned Opc = InFlag.getOpcode(); (void)Opc; in selectNode() local
256 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in selectNode()
257 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in selectNode()
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| D | MipsAnalyzeImmediate.cpp | 15 MipsAnalyzeImmediate::Inst::Inst(unsigned O, unsigned I) : Opc(O), ImmOpnd(I) {} in Inst()
88 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) || in ReplaceADDiuSLLWithLUi()
89 (Seq[1].Opc != SLL) || (Seq[1].ImmOpnd < 16)) in ReplaceADDiuSLLWithLUi()
100 Seq[0].Opc = LUi; in ReplaceADDiuSLLWithLUi()
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| D | MipsSEISelDAGToDAG.cpp | 219 unsigned Opc = InFlag.getOpcode(); (void)Opc; in selectAddESubE() local
221 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in selectAddESubE()
222 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in selectAddESubE()
385 if (Inst->Opc == Mips::LUi64) in selectNode()
386 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd); in selectNode()
389 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, in selectNode()
397 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, in selectNode()
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| D | Mips16InstrInfo.h | 67 virtual unsigned getOppositeBranchOpc(unsigned Opc) const;
112 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const;
115 unsigned Opc) const;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 43 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
343 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode() argument
344 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; in isUncondBranchOpcode()
348 bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode() argument
349 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; in isCondBranchOpcode()
353 bool isJumpTableBranchOpcode(int Opc) { in isJumpTableBranchOpcode() argument
354 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd || in isJumpTableBranchOpcode()
355 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT; in isJumpTableBranchOpcode()
359 bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode() argument
360 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; in isIndirectBranchOpcode()
[all …]
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| D | ARMISelDAGToDAG.cpp | 111 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
114 SDValue &Offset, SDValue &Opc);
116 SDValue &Opc) { in SelectAddrMode2Base() argument
117 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE; in SelectAddrMode2Base()
121 SDValue &Opc) { in SelectAddrMode2ShOp() argument
122 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP; in SelectAddrMode2ShOp()
126 SDValue &Opc) { in SelectAddrMode2() argument
127 SelectAddrMode2Worker(N, Base, Offset, Opc); in SelectAddrMode2()
134 SDValue &Offset, SDValue &Opc);
136 SDValue &Offset, SDValue &Opc);
[all …]
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| D | ARMFastISel.cpp | 523 unsigned Opc; in ARMMaterializeFP() local
526 Opc = ARM::FCONSTD; in ARMMaterializeFP()
529 Opc = ARM::FCONSTS; in ARMMaterializeFP()
532 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), in ARMMaterializeFP()
549 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; in ARMMaterializeFP() local
552 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), in ARMMaterializeFP()
568 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; in ARMMaterializeInt() local
573 TII.get(Opc), ImmReg) in ARMMaterializeInt()
584 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; in ARMMaterializeInt() local
587 TII.get(Opc), ImmReg) in ARMMaterializeInt()
[all …]
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| D | ARMInstrInfo.cpp | 52 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const { in getUnindexedOpcode()
53 switch (Opc) { in getUnindexedOpcode()
123 unsigned Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? in runOnMachineFunction() local
127 TII.get(Opc), GlobalBaseReg) in runOnMachineFunction()
129 if (Opc == ARM::LDRcp) in runOnMachineFunction()
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| D | Thumb1RegisterInfo.cpp | 129 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); in emitThumbRegPlusImmInReg() local
131 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); in emitThumbRegPlusImmInReg()
132 if (Opc != ARM::tADDhirr) in emitThumbRegPlusImmInReg()
143 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, in calcNumMI() argument
148 if (Opc == ARM::tADDrSPi) { in calcNumMI()
182 int Opc = 0; in emitThumbRegPlusImmediate() local
190 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitThumbRegPlusImmediate()
203 Opc = ARM::tADDrSPi; in emitThumbRegPlusImmediate()
212 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitThumbRegPlusImmediate()
217 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; in emitThumbRegPlusImmediate()
[all …]
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| D | Thumb2SizeReduction.cpp | 336 unsigned Opc = MI->getOpcode(); in VerifyLowRegs() local
337 bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA || in VerifyLowRegs()
338 Opc == ARM::t2LDMDB || Opc == ARM::t2LDMIA_UPD || in VerifyLowRegs()
339 Opc == ARM::t2LDMDB_UPD); in VerifyLowRegs()
340 bool isLROk = (Opc == ARM::t2STMIA_UPD || Opc == ARM::t2STMDB_UPD); in VerifyLowRegs()
356 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12)) in VerifyLowRegs()
377 unsigned Opc = Entry.NarrowOpc1; in ReduceLoadStore() local
387 Opc = Entry.NarrowOpc2; in ReduceLoadStore()
445 Opc = Entry.NarrowOpc2; // tPOP_RET in ReduceLoadStore()
460 Opc = Entry.NarrowOpc2; // tPOP or tPUSH in ReduceLoadStore()
[all …]
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| D | Thumb2InstrInfo.cpp | 44 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const { in getUnindexedOpcode()
261 unsigned Opc = 0; in emitT2RegPlusImmediate() local
275 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitT2RegPlusImmediate()
276 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) in emitT2RegPlusImmediate()
283 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri; in emitT2RegPlusImmediate()
296 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri; in emitT2RegPlusImmediate()
300 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in emitT2RegPlusImmediate()
315 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) in emitT2RegPlusImmediate()
612 unsigned Opc = MI->getOpcode(); in getITInstrPredicate() local
613 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc) in getITInstrPredicate()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonCFGOptimizer.cpp | 60 static bool IsConditionalBranch(int Opc) { in IsConditionalBranch() argument
61 return (Opc == Hexagon::JMP_t) || (Opc == Hexagon::JMP_f) in IsConditionalBranch()
62 || (Opc == Hexagon::JMP_tnew_t) || (Opc == Hexagon::JMP_fnew_t); in IsConditionalBranch()
66 static bool IsUnconditionalJump(int Opc) { in IsUnconditionalJump() argument
67 return (Opc == Hexagon::JMP); in IsUnconditionalJump()
113 int Opc = MI->getOpcode(); in runOnMachineFunction() local
114 if (IsConditionalBranch(Opc)) { in runOnMachineFunction()
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| D | HexagonSplitConst32AndConst64.cpp | 83 int Opc = MI->getOpcode(); in runOnMachineFunction() local
84 if (Opc == Hexagon::CONST32_set) { in runOnMachineFunction()
97 else if (Opc == Hexagon::CONST32_set_jt) { in runOnMachineFunction()
110 else if (Opc == Hexagon::CONST32_Label) { in runOnMachineFunction()
123 else if (Opc == Hexagon::CONST32_Int_Real) { in runOnMachineFunction()
134 else if (Opc == Hexagon::CONST64_Int_Real) { in runOnMachineFunction()
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| /external/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 107 unsigned Opc = MBBI->getOpcode(); in findDeadCallerSavedReg() local
108 switch (Opc) { in findDeadCallerSavedReg()
152 unsigned Opc; in emitSPUpdate() local
154 Opc = getLEArOpcode(IsLP64); in emitSPUpdate()
156 Opc = isSub in emitSPUpdate()
171 Opc = isSub in emitSPUpdate()
174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc)) in emitSPUpdate()
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr), in emitSPUpdate()
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in emitSPUpdate()
209 unsigned Opc = PI->getOpcode(); in mergeSPUpdatesUp() local
[all …]
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| D | X86ISelDAGToDAG.cpp | 184 SDNode *SelectGather(SDNode *N, unsigned Opc);
185 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
1561 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) { in SelectAtomic64() argument
1573 SDNode *ResNode = CurDAG->getMachineNode(Opc, SDLoc(Node), in SelectAtomic64()
1795 unsigned Opc = 0; in SelectAtomicLoadArith() local
1800 Opc = AtomicOpcTbl[Op][ConstantI8]; in SelectAtomicLoadArith()
1802 Opc = AtomicOpcTbl[Op][I8]; in SelectAtomicLoadArith()
1807 Opc = AtomicOpcTbl[Op][SextConstantI16]; in SelectAtomicLoadArith()
1809 Opc = AtomicOpcTbl[Op][ConstantI16]; in SelectAtomicLoadArith()
1811 Opc = AtomicOpcTbl[Op][I16]; in SelectAtomicLoadArith()
[all …]
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| D | X86FastISel.cpp | 87 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
182 unsigned Opc = 0; in X86FastEmitLoad() local
188 Opc = X86::MOV8rm; in X86FastEmitLoad()
192 Opc = X86::MOV16rm; in X86FastEmitLoad()
196 Opc = X86::MOV32rm; in X86FastEmitLoad()
201 Opc = X86::MOV64rm; in X86FastEmitLoad()
206 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm; in X86FastEmitLoad()
209 Opc = X86::LD_Fp32m; in X86FastEmitLoad()
215 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm; in X86FastEmitLoad()
218 Opc = X86::LD_Fp64m; in X86FastEmitLoad()
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| D | X86InstrInfo.cpp | 1718 unsigned Opc = Orig->getOpcode(); in reMaterialize() local
1719 if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) { in reMaterialize()
1767 unsigned Opc, bool AllowSP, in classifyLEAReg() argument
1773 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass; in classifyLEAReg()
1775 RC = Opc != X86::LEA32r ? in classifyLEAReg()
1782 if (Opc != X86::LEA64_32r) { in classifyLEAReg()
1854 unsigned Opc, leaInReg; in convertToThreeAddressWithLEA() local
1856 Opc = X86::LEA64_32r; in convertToThreeAddressWithLEA()
1859 Opc = X86::LEA32r; in convertToThreeAddressWithLEA()
1877 get(Opc), leaOutReg); in convertToThreeAddressWithLEA()
[all …]
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| /external/llvm/utils/TableGen/ |
| D | FixedLenDecoderEmitter.cpp | 421 void SingletonExists(unsigned Opc) const;
439 unsigned Opc) const;
441 bool doesOpcodeNeedPredicate(unsigned Opc) const;
444 unsigned Opc) const;
447 unsigned Opc) const;
451 unsigned Opc) const;
460 void emitDecoder(raw_ostream &OS, unsigned Indentation, unsigned Opc) const;
461 unsigned getDecoderIndex(DecoderSet &Decoders, unsigned Opc) const;
819 unsigned Opc = decodeULEB128(Buffer); in emitTable() local
831 << NumberedInstructions->at(Opc)->TheDef->getName() << "\n"; in emitTable()
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 482 enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc; in DecodeBitfieldInstruction() local
483 Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2); in DecodeBitfieldInstruction()
494 if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); in DecodeBitfieldInstruction()
499 if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder); in DecodeBitfieldInstruction()
504 assert(!(ImmS == 31 && !SF && Opc != BFM) in DecodeBitfieldInstruction()
506 assert(!(ImmS == 63 && SF && Opc != BFM) in DecodeBitfieldInstruction()
510 if (Opc == SBFM && ImmR == 0) { in DecodeBitfieldInstruction()
513 } else if (Opc == UBFM && ImmR == 0) { in DecodeBitfieldInstruction()
517 if (Opc == UBFM) { in DecodeBitfieldInstruction()
534 switch (Opc) { in DecodeBitfieldInstruction()
[all …]
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| /external/llvm/include/llvm/IR/ |
| D | InstrTypes.h | 194 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2,
196 BinaryOperator *BO = Create(Opc, V1, V2, Name);
200 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2,
202 BinaryOperator *BO = Create(Opc, V1, V2, Name, BB);
206 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2,
208 BinaryOperator *BO = Create(Opc, V1, V2, Name, I);
213 static BinaryOperator *CreateNUW(BinaryOps Opc, Value *V1, Value *V2,
215 BinaryOperator *BO = Create(Opc, V1, V2, Name);
219 static BinaryOperator *CreateNUW(BinaryOps Opc, Value *V1, Value *V2,
221 BinaryOperator *BO = Create(Opc, V1, V2, Name, BB);
[all …]
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| /external/clang/include/clang/AST/ |
| D | Expr.h | 1641 unsigned Opc : 5;
1654 Opc(opc), Loc(l), Val(input) {} in UnaryOperator()
1658 : Expr(UnaryOperatorClass, Empty), Opc(UO_AddrOf) { } in UnaryOperator()
1660 Opcode getOpcode() const { return static_cast<Opcode>(Opc); } in getOpcode()
1661 void setOpcode(Opcode O) { Opc = O; } in setOpcode()
1717 static OverloadedOperatorKind getOverloadedOperator(Opcode Opc);
2887 unsigned Opc : 6;
2910 Opc(opc), FPContractable(fpContractable), OpLoc(opLoc) { in BinaryOperator()
2919 : Expr(BinaryOperatorClass, Empty), Opc(BO_Comma) { } in BinaryOperator()
2925 Opcode getOpcode() const { return static_cast<Opcode>(Opc); } in getOpcode()
[all …]
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 407 static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
410 bool isSub = Opc == sub;
442 static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset,
444 bool isSub = Opc == sub;
492 static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) { in getAM5Opc() argument
493 bool isSub = Opc == sub; in getAM5Opc()
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