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Searched refs:RC (Results 1 – 25 of 275) sorted by relevance

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/external/llvm/lib/Target/NVPTX/
DNVPTXRegisterInfo.cpp29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { in getNVPTXRegClassName() argument
30 if (RC == &NVPTX::Float32RegsRegClass) { in getNVPTXRegClassName()
33 if (RC == &NVPTX::Float64RegsRegClass) { in getNVPTXRegClassName()
35 } else if (RC == &NVPTX::Int64RegsRegClass) { in getNVPTXRegClassName()
37 } else if (RC == &NVPTX::Int32RegsRegClass) { in getNVPTXRegClassName()
39 } else if (RC == &NVPTX::Int16RegsRegClass) { in getNVPTXRegClassName()
41 } else if (RC == &NVPTX::Int1RegsRegClass) { in getNVPTXRegClassName()
43 } else if (RC == &NVPTX::SpecialRegsRegClass) { in getNVPTXRegClassName()
51 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { in getNVPTXRegClassStr() argument
52 if (RC == &NVPTX::Float32RegsRegClass) { in getNVPTXRegClassStr()
[all …]
/external/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h68 void compute(const TargetRegisterClass *RC) const;
71 const RCInfo &get(const TargetRegisterClass *RC) const { in get() argument
72 const RCInfo &RCI = RegClass[RC->getID()]; in get()
74 compute(RC); in get()
87 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs() argument
88 return get(RC).NumRegs; in getNumAllocatableRegs()
94 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder() argument
95 return get(RC); in getOrder()
104 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass() argument
105 return get(RC).ProperSubClass; in isProperSubClass()
[all …]
DFastISel.h257 const TargetRegisterClass *RC);
262 const TargetRegisterClass *RC,
268 const TargetRegisterClass *RC,
275 const TargetRegisterClass *RC,
283 const TargetRegisterClass *RC,
289 const TargetRegisterClass *RC,
296 const TargetRegisterClass *RC,
303 const TargetRegisterClass *RC,
311 const TargetRegisterClass *RC,
319 const TargetRegisterClass *RC,
[all …]
/external/llvm/lib/Target/Mips/
DMipsMachineFunction.cpp36 const TargetRegisterClass *RC; in getGlobalBaseReg() local
38 RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass; in getGlobalBaseReg()
40 RC = ST.isABI_N64() ? in getGlobalBaseReg()
43 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC); in getGlobalBaseReg()
54 const TargetRegisterClass *RC; in getMips16SPAliasReg() local
55 RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass; in getMips16SPAliasReg()
56 return Mips16SPAliasReg = MF.getRegInfo().createVirtualRegister(RC); in getMips16SPAliasReg()
62 const TargetRegisterClass *RC = ST.isABI_N64() ? in createEhDataRegsFI() local
65 EhDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(RC->getSize(), in createEhDataRegsFI()
66 RC->getAlignment(), false); in createEhDataRegsFI()
DMipsSEFrameLowering.cpp123 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
124 unsigned VR = MRI.createVirtualRegister(RC); in expandLoadCCond()
127 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); in expandLoadCCond()
143 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
144 unsigned VR = MRI.createVirtualRegister(RC); in expandStoreCCond()
149 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); in expandStoreCCond()
166 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
167 unsigned VR0 = MRI.createVirtualRegister(RC); in expandLoadACC()
168 unsigned VR1 = MRI.createVirtualRegister(RC); in expandLoadACC()
175 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0); in expandLoadACC()
[all …]
DMipsInstrFPU.td92 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
94 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
96 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> {
145 class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
147 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
148 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI> {
153 class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
155 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
156 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI> {
161 class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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DMipsInstrInfo.h88 const TargetRegisterClass *RC, in storeRegToStackSlot() argument
90 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0); in storeRegToStackSlot()
96 const TargetRegisterClass *RC, in loadRegFromStackSlot() argument
98 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0); in loadRegFromStackSlot()
104 const TargetRegisterClass *RC,
111 const TargetRegisterClass *RC,
DMipsInstrInfo.td1248 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1249 MipsPat<(MipsWrapper RC:$gp, node:$in),
1250 (ADDiuOp RC:$gp, node:$in)>;
1284 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1287 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1288 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1289 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1290 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1292 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1293 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
[all …]
DMipsSEInstrInfo.cpp180 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, in storeRegToStack() argument
188 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
190 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
192 else if (Mips::ACRegsRegClass.hasSubClassEq(RC)) in storeRegToStack()
194 else if (Mips::ACRegsDSPRegClass.hasSubClassEq(RC)) in storeRegToStack()
196 else if (Mips::ACRegs128RegClass.hasSubClassEq(RC)) in storeRegToStack()
198 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) in storeRegToStack()
200 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
202 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
204 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
[all …]
/external/llvm/lib/CodeGen/
DTargetRegisterInfo.cpp79 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { in getAllocatableClass()
80 if (!RC || RC->isAllocatable()) in getAllocatableClass()
81 return RC; in getAllocatableClass()
83 const unsigned *SubClass = RC->getSubClassMask(); in getAllocatableClass()
110 const TargetRegisterClass* RC = *I; in getMinimalPhysRegClass() local
111 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) && in getMinimalPhysRegClass()
112 (!BestRC || BestRC->hasSubClass(RC))) in getMinimalPhysRegClass()
113 BestRC = RC; in getMinimalPhysRegClass()
123 const TargetRegisterClass *RC, BitVector &R){ in getAllocatableSetForRC() argument
124 assert(RC->isAllocatable() && "invalid for nonallocatable sets"); in getAllocatableSetForRC()
[all …]
DRegisterClassInfo.cpp78 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { in compute()
79 RCInfo &RCI = RegClass[RC->getID()]; in compute()
82 unsigned NumRegs = RC->getNumRegs(); in compute()
95 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF); in compute()
132 if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC)) in compute()
133 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
140 dbgs() << "AllocationOrder(" << RC->getName() << ") = ["; in compute()
154 const TargetRegisterClass *RC = 0; in computePSetLimit() local
169 if (!RC || NUnits > NumRCUnits) { in computePSetLimit()
170 RC = *RI; in computePSetLimit()
[all …]
DLiveStackAnalysis.cpp58 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval() argument
64 S2RCMap.insert(std::make_pair(Slot, RC)); in getOrCreateInterval()
68 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); in getOrCreateInterval()
80 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
81 if (RC) in print()
82 OS << " [" << RC->getName() << "]\n"; in print()
DRegisterScavenging.cpp258 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const { in FindUnusedReg()
259 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); in FindUnusedReg()
271 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) { in getRegsAvailable() argument
273 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); in getRegsAvailable()
361 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, in scavengeRegister() argument
366 TRI->getAllocatableSet(*I->getParent()->getParent(), RC); in scavengeRegister()
380 BitVector Available = getRegsAvailable(RC); in scavengeRegister()
412 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) { in scavengeRegister()
417 RC, TRI); in scavengeRegister()
425 RC, TRI); in scavengeRegister()
/external/llvm/utils/release/
Dtest-release.sh28 RC=""
68 -rc | --rc | -RC | --RC )
70 RC="rc$1"
73 RC=final
134 if [ -z "$RC" ]; then
154 BuildDir=$BuildDir/$RC
189 if ! svn ls $Base_url/$proj/tags/RELEASE_$Release_no_dot/$RC > /dev/null 2>&1 ; then
190 echo "llvm $Release release candidate $RC doesn't exist!"
201 echo "# Exporting $proj $Release-RC$RC sources"
202 if ! svn export -q $Base_url/$proj/tags/RELEASE_$Release_no_dot/$RC $proj.src ; then
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/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h125 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass() argument
126 return RC != this && hasSubClassEq(RC); in hasSubClass()
131 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq() argument
132 unsigned ID = RC->getID(); in hasSubClassEq()
138 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass() argument
139 return RC->hasSubClass(this); in hasSuperClass()
144 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq() argument
145 return RC->hasSubClassEq(this); in hasSuperClassEq()
314 getAllocatableClass(const TargetRegisterClass *RC) const;
320 const TargetRegisterClass *RC = NULL) const;
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/external/llvm/lib/Target/X86/
DX86InstrFMA.td119 RegisterClass RC, ValueType OpVT, PatFrag mem_frag,
122 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
123 (ins RC:$src1, RC:$src2, RC:$src3),
126 [(set RC:$dst,
127 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
129 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
130 (ins RC:$src1, RC:$src2, x86memop:$src3),
133 [(set RC:$dst,
134 (OpVT (OpNode RC:$src2, RC:$src1,
140 RegisterClass RC> {
[all …]
/external/llvm/utils/TableGen/
DRegisterInfoEmitter.cpp170 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i]; in EmitRegUnitPressure() local
171 const CodeGenRegister::Set &Regs = RC.getMembers(); in EmitRegUnitPressure()
176 RC.buildRegUnitSet(RegUnits); in EmitRegUnitPressure()
180 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
853 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runMCDesc() local
854 ArrayRef<Record*> Order = RC.getOrder(); in runMCDesc()
857 std::string Name = RC.getName(); in runMCDesc()
887 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runMCDesc() local
891 assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large."); in runMCDesc()
892 assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large."); in runMCDesc()
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/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp98 const TargetRegisterClass *RC);
100 const TargetRegisterClass *RC);
157 const TargetRegisterClass *RC) { in PPCMaterialize32BitInt() argument
161 unsigned ResultReg = createResultReg(RC); in PPCMaterialize32BitInt()
162 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCMaterialize32BitInt()
170 unsigned TmpReg = createResultReg(RC); in PPCMaterialize32BitInt()
189 const TargetRegisterClass *RC) { in PPCMaterialize64BitInt() argument
210 unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC); in PPCMaterialize64BitInt()
218 TmpReg2 = createResultReg(RC); in PPCMaterialize64BitInt()
226 TmpReg3 = createResultReg(RC); in PPCMaterialize64BitInt()
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/external/llvm/lib/Target/R600/
DSIFixSGPRCopies.cpp117 const TargetRegisterClass *RC = MRI.getRegClass(Reg); in inferRegClass() local
122 RC = TRI->getCommonSubClass(RC, inferRegClass(TRI, MRI, in inferRegClass()
128 return RC; in inferRegClass()
145 const TargetRegisterClass *RC = inferRegClass(TRI, MRI, Reg); in runOnMachineFunction() local
146 if (RC == &AMDGPU::VSrc_32RegClass) { in runOnMachineFunction()
/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp370 const TargetRegisterClass *RC = *I; in regPressureDelta() local
371 RegBalance += rawRegPressureDelta(SU, RC->getID()); in regPressureDelta()
377 const TargetRegisterClass *RC = *I; in regPressureDelta() local
378 if ((RegPressure[RC->getID()] + in regPressureDelta()
379 rawRegPressureDelta(SU, RC->getID()) > 0) && in regPressureDelta()
380 (RegPressure[RC->getID()] + in regPressureDelta()
381 rawRegPressureDelta(SU, RC->getID()) >= RegLimit[RC->getID()])) in regPressureDelta()
382 RegBalance += rawRegPressureDelta(SU, RC->getID()); in regPressureDelta()
491 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
492 if (RC) in scheduledNode()
[all …]
/external/llvm/test/TableGen/
Dusevalname.td17 multiclass shuffle<Reg RC> {
18 def rri : Instr<[(set RC:$dst, (shufp:$src3
19 RC:$src1, RC:$src2))]>;
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.h46 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
51 getLargestLegalSuperClass(const TargetRegisterClass *RC) const { in getLargestLegalSuperClass()
52 if (RC == &AArch64::tcGPR64RegClass) in getLargestLegalSuperClass()
55 return RC; in getLargestLegalSuperClass()
/external/clang/lib/AST/
DRawCommentList.cpp211 void RawCommentList::addComment(const RawComment &RC, in addComment() argument
213 if (RC.isInvalid()) in addComment()
220 RC.getSourceRange().getBegin())) { in addComment()
229 RC.getSourceRange().getBegin())) in addComment()
233 PrevCommentEndLoc = RC.getSourceRange().getEnd(); in addComment()
236 if (RC.isOrdinary()) in addComment()
242 Comments.push_back(new (Allocator) RawComment(RC)); in addComment()
248 const RawComment &C2 = RC; in addComment()
262 RC.isParseAllComments()); in addComment()
267 Comments.push_back(new (Allocator) RawComment(RC)); in addComment()
/external/llvm/lib/Target/ARM/
DThumb1InstrInfo.cpp54 const TargetRegisterClass *RC, in storeRegToStackSlot() argument
56 assert((RC == &ARM::tGPRRegClass || in storeRegToStackSlot()
60 if (RC == &ARM::tGPRRegClass || in storeRegToStackSlot()
82 const TargetRegisterClass *RC, in loadRegFromStackSlot() argument
84 assert((RC == &ARM::tGPRRegClass || in loadRegFromStackSlot()
88 if (RC == &ARM::tGPRRegClass || in loadRegFromStackSlot()
/external/llvm/include/llvm/IR/
DInlineAsm.h254 static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) {
256 ++RC;
257 assert(RC <= 0x7fff && "Too large register class ID");
259 return InputFlag | (RC << 16);
293 static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) {
301 RC = High - 1;

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