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Searched refs:Rn (Results 1 – 25 of 36) sorted by relevance

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/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td337 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTB_operand:$Imm3),
338 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
339 [(opfrag exts.ty:$Rn, (shl exts.uxtb, UXTB_operand:$Imm3))],
342 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTH_operand:$Imm3),
343 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
344 [(opfrag exts.ty:$Rn, (shl exts.uxth, UXTH_operand:$Imm3))],
347 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTW_operand:$Imm3),
348 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
349 [(opfrag exts.ty:$Rn, (shl exts.uxtw, UXTW_operand:$Imm3))],
353 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTB_operand:$Imm3),
[all …]
DAArch64InstrNEON.td55 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
56 asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
58 (v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
62 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
63 asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
65 (v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
77 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
78 asmop # "\t$Rd.4h, $Rn.4h, $Rm.4h",
80 (v4i16 (opnode (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))))],
84 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
[all …]
DAArch64InstrFormats.td92 bits<5> Rn;
94 let Inst{9-5} = Rn;
101 bits<5> Rn;
103 let Inst{9-5} = Rn;
106 // Instructions taking Rt,Rt2,Rn
144 // Rn inherited in 9-5
178 // Rn inherited in 9-5
193 // Rn inherited in 9-5
212 // Inherit Rn in 9-5
250 bits<5> Rn;
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td279 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
285 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
310 bits<4> Rn;
322 bits<4> Rn;
325 let Inst{19-16} = Rn;
361 bits<4> Rn;
364 let Inst{19-16} = Rn;
394 bits<4> Rn;
397 let Inst{19-16} = Rn;
406 bits<4> Rn;
[all …]
DARMInstrInfo.td1043 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1050 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1051 iii, opc, "\t$Rd, $Rn, $imm",
1052 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1055 bits<4> Rn;
1058 let Inst{19-16} = Rn;
1063 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1064 iir, opc, "\t$Rd, $Rn, $Rm",
1065 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1068 bits<4> Rn;
[all …]
DARMInstrThumb.td354 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
365 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
386 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
387 "add", "\t$Rdn, $sp, $Rn", []>,
398 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
703 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
704 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
705 bits<3> Rn;
707 let Inst{10-8} = Rn;
716 "$Rn = $wb", IIC_iLoad_mu>,
[all …]
DARMInstrNEON.td568 : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn),
570 [(set DPair:$dst, (v2f64 (load GPR:$Rn)))]>;
575 : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
577 [(store (v2f64 DPair:$src), GPR:$Rn)]>;
625 (ins addrmode6:$Rn), IIC_VLD1,
626 "vld1", Dt, "$Vd, $Rn", "", []> {
628 let Inst{4} = Rn{4};
633 (ins addrmode6:$Rn), IIC_VLD1x2,
634 "vld1", Dt, "$Vd, $Rn", "", []> {
636 let Inst{5-4} = Rn{5-4};
[all …]
DARMInstrFormats.td75 // The instruction has an Rn register operand.
77 // it doesn't have a Rn operand.
600 bits<4> Rn;
603 let Inst{19-16} = Rn;
618 bits<4> Rn;
621 let Inst{19-16} = Rn;
634 // {17-14} Rn
658 let Inst{19-16} = addr{12-9}; // Rn
688 // {12-9} Rn
698 let Inst{19-16} = addr; // Rn
[all …]
DARMSchedule.td18 // Rd <- ADD Rn, Rm, <shift> Rs
20 // 2 | Rn: 1 Rm: 4 Rs: 4 | uop T0, Rm, Rs - P01 - 3
21 // | | uopc Rd, Rn, T0 - P01 - 1
24 // and one cycle after the result in Rn is available. The micro-ops can execute
27 // that the resource P01 is needed and that the latency to Rn is different than
28 // the latency to Rm and Rs. The scheduler can decrease Rn's producer latency by
DARMInstrVFP.td130 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
132 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
138 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
141 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
147 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
150 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
158 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
160 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
170 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
173 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
[all …]
DARMBaseInstrInfo.cpp2525 unsigned Rn = MI->getOperand(2).getReg(); in getNumMicroOpsSwiftLdSt() local
2529 return (Rt == Rn) ? 3 : 2; in getNumMicroOpsSwiftLdSt()
2549 unsigned Rn = MI->getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
2553 return (Rt == Rn) ? 4 : 3; in getNumMicroOpsSwiftLdSt()
2558 unsigned Rn = MI->getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
2559 return (Rt == Rn) ? 4 : 3; in getNumMicroOpsSwiftLdSt()
2594 unsigned Rn = MI->getOperand(2).getReg(); in getNumMicroOpsSwiftLdSt() local
2595 return (Rt == Rn) ? 3 : 2; in getNumMicroOpsSwiftLdSt()
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1303 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeCopMemInstruction() local
1348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeCopMemInstruction()
1444 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeAddrMode2IdxInstruction() local
1463 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1483 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1490 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1504 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
1549 unsigned Rn = fieldFromInstruction(Val, 13, 4); in DecodeSORegMemOperand() local
1574 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeSORegMemOperand()
1594 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeAddrMode3Instruction() local
[all …]
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp475 unsigned Rn = fieldFromInstruction(Insn, 5, 5); in DecodeBitfieldInstruction() local
495 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); in DecodeBitfieldInstruction()
500 DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder); in DecodeBitfieldInstruction()
569 unsigned Rn = fieldFromInstruction(Insn, 5, 5); in DecodeFMOVLaneInstruction() local
574 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); in DecodeFMOVLaneInstruction()
577 DecodeVPR128RegisterClass(Inst, Rn, Address, Decoder); in DecodeFMOVLaneInstruction()
593 unsigned Rn = fieldFromInstruction(Insn, 5, 5); in DecodeLDSTPairInstruction() local
607 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); in DecodeLDSTPairInstruction()
616 if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn)) in DecodeLDSTPairInstruction()
661 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); in DecodeLDSTPairInstruction()
[all …]
/external/qemu/
Dtrace.c896 int Rn = (insn >> 12) & 15; in get_insn_ticks_arm() local
899 result += _interlock_use(Rn); in get_insn_ticks_arm()
901 if (Rn != 0) /* UNDEFINED */ in get_insn_ticks_arm()
934 int Rn = (insn >> 16) & 15; in get_insn_ticks_arm() local
936 result += _interlock_use(Rn) + _interlock_use(Rm); in get_insn_ticks_arm()
943 int Rn = (insn >> 16) & 15; in get_insn_ticks_arm() local
945 result += _interlock_use(Rn); in get_insn_ticks_arm()
957 int Rn = (insn >> 16) & 15; in get_insn_ticks_arm() local
959 result += _interlock_use(Rn) + _interlock_use(Rm); in get_insn_ticks_arm()
970 int Rn = (insn >> 16) & 15; in get_insn_ticks_arm() local
[all …]
Darm-dis.c3450 unsigned int Rn = (given & 0x000f0000) >> 16; in print_insn_thumb32() local
3458 func (stream, "[%s", arm_regnames[Rn]); in print_insn_thumb32()
3461 else if (Rn == 15) /* 12-bit negative immediate offset */ in print_insn_thumb32()
3517 if (Rn == 15) in print_insn_thumb32()
3531 unsigned int Rn = (given & 0x000f0000) >> 16; in print_insn_thumb32() local
3534 func (stream, "[%s", arm_regnames[Rn]); in print_insn_thumb32()
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-thumbv7.txt69 # Writeback is not allowed is Rn is in the target register list.
86 # if Rn = '1111' then SEE LDRD (literal)
183 # invalid STRi12 Rn=PC
188 # invalid STRi8 Rn=PC
193 # invalid STRs Rn=PC
198 # invalid STRBi12 Rn=PC
203 # invalid STRBi8 Rn=PC
208 # invalid STRBs Rn=PC
213 # invalid STRHi12 Rn=PC
218 # invalid STRHi8 Rn=PC
[all …]
/external/chromium_org/v8/src/arm/
Ddisasm-arm.cc114 void FormatNeonMemory(int Rn, int align, int Rm);
440 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) { in FormatNeonMemory() argument
442 "[r%d", Rn); in FormatNeonMemory()
1595 int Rn = instr->VnValue(); in DecodeSpecialCondition() local
1604 FormatNeonMemory(Rn, align, Rm); in DecodeSpecialCondition()
1608 int Rn = instr->VnValue(); in DecodeSpecialCondition() local
1617 FormatNeonMemory(Rn, align, Rm); in DecodeSpecialCondition()
1625 int Rn = instr->Bits(19, 16); in DecodeSpecialCondition() local
1629 "pld [r%d]", Rn); in DecodeSpecialCondition()
1632 "pld [r%d, #-%d]", Rn, offset); in DecodeSpecialCondition()
[all …]
Dsimulator-arm.cc3504 int Rn = instr->VnValue(); in DecodeSpecialCondition() local
3507 int32_t address = get_register(Rn); in DecodeSpecialCondition()
3537 set_register(Rn, address); in DecodeSpecialCondition()
3539 set_register(Rn, get_register(Rn) + get_register(Rm)); in DecodeSpecialCondition()
3545 int Rn = instr->VnValue(); in DecodeSpecialCondition() local
3548 int32_t address = get_register(Rn); in DecodeSpecialCondition()
3578 set_register(Rn, address); in DecodeSpecialCondition()
3580 set_register(Rn, get_register(Rn) + get_register(Rm)); in DecodeSpecialCondition()
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp740 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getThumbAddrModeRegRegOpValue() local
742 return (Rm << 3) | Rn; in getThumbAddrModeRegRegOpValue()
956 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getLdStSORegOpValue() local
975 Binary |= Rn << 13; in getLdStSORegOpValue()
991 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getAddrMode2OpValue() local
993 Binary |= Rn << 14; in getAddrMode2OpValue()
1063 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. in getAddrMode3OpValue() local
1071 return (Rn << 9) | (1 << 13); in getAddrMode3OpValue()
1073 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getAddrMode3OpValue() local
1081 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13); in getAddrMode3OpValue()
[all …]
/external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/es-ES/
Des-ES_kdt_g2p.pkb11 �U�����9���rEL_^���ZdM��e���8�X��4�չE%Mg�>�h�i�>K'`(�>~B`�Z�,�Rn
/external/llvm/test/CodeGen/AArch64/
Dzero-reg.ll23 ; instruction (0b11111 in the Rn field would mean "sp").
/external/chromium_org/third_party/openssl/openssl/crypto/pkcs7/
Des1.pem22 Rn/KOhHaYP2VzAh40gQIvKMAAWh9oFsEEIMwIoOmLwLH5wf+8QdbDhoECH8HwZt9a12dBAjL
/external/openssl/crypto/pkcs7/
Des1.pem22 Rn/KOhHaYP2VzAh40gQIvKMAAWh9oFsEEIMwIoOmLwLH5wf+8QdbDhoECH8HwZt9a12dBAjL
/external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/it-IT/
Dit-IT_cm0_kdt_dur.pkb76 �!6Rn���zp���!YH7�������9�D�'��r��Zld�X�Tj�����
/external/llvm/test/MC/ARM/
Dthumb2-narrow-dp.ll5 // OP{S}{<c>}{<q>} {<Rd>,} <Rn>, <Rm>
7 // - Rd == Rn
8 // - Rd, Rn and Rm are < r8
11 // - Rd == Rn || Rd == Rm
12 // - Rd, Rn and Rm are < r8

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