| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 336 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName() argument
337 assert(SubIdx && SubIdx < getNumSubRegIndices() && in getSubRegIndexName()
339 return SubRegIndexNames[SubIdx-1]; in getSubRegIndexName()
361 unsigned getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask() argument
363 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); in getSubRegIndexLaneMask()
364 return SubRegIndexLaneMasks[SubIdx]; in getSubRegIndexLaneMask()
457 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
459 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); in getMatchingSuperReg()
881 unsigned SubIdx; variable
885 : TRI(tri), Reg(reg), SubIdx(subidx) {} in TRI()
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| D | TargetInstrInfo.h | 115 unsigned &SubIdx) const { in isCoalescableExtInstr() argument
191 unsigned DestReg, unsigned SubIdx,
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 317 getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg() argument
318 return SubClassWithSubReg.lookup(SubIdx); in getSubClassWithSubReg()
321 void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg() argument
323 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
328 void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const;
331 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass() argument
333 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
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| D | CodeGenRegisters.cpp | 480 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); in computeSecondarySubRegs() local
481 if (!SubIdx) in computeSecondarySubRegs()
484 NewIdx->addComposite(SI->first, SubIdx); in computeSecondarySubRegs()
899 CodeGenRegisterClass::getSuperRegClasses(CodeGenSubRegIndex *SubIdx, in getSuperRegClasses() argument
903 FindI = SuperRegClasses.find(SubIdx); in getSuperRegClasses()
1495 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); in pruneUnitSets() local
1496 SubIdx != EndIdx; ++SubIdx) { in pruneUnitSets()
1497 const RegUnitSet &SubSet = RegUnitSets[SubIdx]; in pruneUnitSets()
1500 if (SuperIdx == SubIdx) in pruneUnitSets()
1509 DEBUG(dbgs() << "UnitSet " << SubIdx << " subsumed by " << SuperIdx in pruneUnitSets()
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2RegisterInfo.cpp | 37 unsigned DestReg, unsigned SubIdx, in emitLoadConstPool() argument
49 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
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| D | Thumb2RegisterInfo.h | 35 unsigned DestReg, unsigned SubIdx, int Val,
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| D | Thumb1RegisterInfo.h | 41 unsigned DestReg, unsigned SubIdx, int Val,
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| D | ARMBaseInstrInfo.h | 130 unsigned DestReg, unsigned SubIdx,
139 unsigned SubIdx, unsigned State,
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| D | ARMBaseRegisterInfo.h | 164 unsigned DestReg, unsigned SubIdx,
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| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 150 unsigned SrcReg, DstReg, SubIdx; in INITIALIZE_PASS_DEPENDENCY() local
151 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) in INITIALIZE_PASS_DEPENDENCY()
165 DstRC = TM->getRegisterInfo()->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
175 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0; in INITIALIZE_PASS_DEPENDENCY()
206 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
286 .addReg(DstReg, 0, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
289 Copy->getOperand(0).setSubReg(SubIdx); in INITIALIZE_PASS_DEPENDENCY()
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| D | ExpandPostRAPseudos.cpp | 88 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
90 assert(SubIdx != 0 && "Invalid index for insert_subreg"); in LowerSubregToReg()
91 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
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| D | TargetRegisterInfo.cpp | 47 if (SubIdx) { in print()
49 OS << ':' << TRI->getSubRegIndexName(SubIdx); in print()
51 OS << ":sub(" << SubIdx << ')'; in print()
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| D | MachineCopyPropagation.cpp | 120 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); in isNopCopy() local
121 if (!SubIdx) in isNopCopy()
123 return SubIdx == TRI->getSubRegIndex(SrcDef, Src); in isNopCopy()
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| D | LiveDebugVariables.h | 45 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx);
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| D | RegisterCoalescer.cpp | 180 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
944 unsigned SubIdx) { in updateRegDefsUses() argument
965 if (DstInt && !Reads && SubIdx) in updateRegDefsUses()
975 if (SubIdx && MO.isDef()) in updateRegDefsUses()
981 MO.substVirtReg(DstReg, SubIdx, *TRI); in updateRegDefsUses()
1283 unsigned SubIdx; member in __anon0e7ecfb60211::JoinVals
1389 : LI(li), SubIdx(subIdx), NewVNInfo(newVNInfo), CP(cp), LIS(lis), in JoinVals()
1428 TRI->composeSubRegIndices(SubIdx, MO->getSubReg())); in computeWriteLanes()
1474 V.ValidLanes = V.WriteLanes = TRI->getSubRegIndexLaneMask(SubIdx); in analyzeValue()
1642 if ((TRI->getSubRegIndexLaneMask(Other.SubIdx) & ~V.WriteLanes) == 0) in analyzeValue()
[all …]
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| D | MachineRegisterInfo.cpp | 82 if (unsigned SubIdx = I.getOperand().getSubReg()) { in recomputeRegClass() local
85 SubIdx); in recomputeRegClass()
87 NewRC = getTargetRegisterInfo()->getSubClassWithSubReg(NewRC, SubIdx); in recomputeRegClass()
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| D | MachineInstr.cpp | 69 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, in substVirtReg() argument
72 if (SubIdx && getSubReg()) in substVirtReg()
73 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
75 if (SubIdx) in substVirtReg()
76 setSubReg(SubIdx); in substVirtReg()
1201 unsigned SubIdx, in substituteRegister() argument
1204 if (SubIdx) in substituteRegister()
1205 ToReg = RegInfo.getSubReg(ToReg, SubIdx); in substituteRegister()
1217 MO.substVirtReg(ToReg, SubIdx, RegInfo); in substituteRegister()
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| D | MachineVerifier.cpp | 889 unsigned SubIdx = MO->getSubReg(); in visitMachineOperand() local
892 if (SubIdx) { in visitMachineOperand()
907 if (SubIdx) { in visitMachineOperand()
909 TRI->getSubClassWithSubReg(RC, SubIdx); in visitMachineOperand()
913 << " does not support subreg index " << SubIdx << "\n"; in visitMachineOperand()
919 << " does not fully support subreg index " << SubIdx << "\n"; in visitMachineOperand()
925 if (SubIdx) { in visitMachineOperand()
932 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
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| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) in getMatchingSuperReg()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 424 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg() argument
427 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
440 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
475 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
484 SubIdx == DefSubIdx && in EmitSubregNode()
499 VReg = ConstrainForSubReg(VReg, SubIdx, in EmitSubregNode()
509 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); in EmitSubregNode()
516 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
533 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
554 MIB.addImm(SubIdx); in EmitSubregNode()
[all …]
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| D | InstrEmitter.h | 87 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
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| /external/llvm/lib/Target/R600/ |
| D | SIInstrInfo.cpp | 159 while (unsigned SubIdx = *SubIndices++) { in copyPhysReg() local
161 get(Opcode), RI.getSubReg(DestReg, SubIdx)); in copyPhysReg()
163 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc)); in copyPhysReg()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 88 unsigned &SubIdx) const { in isCoalescableExtInstr()
95 SubIdx = PPC::sub_32; in isCoalescableExtInstr()
494 unsigned SubIdx; in insertSelect() local
498 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break; in insertSelect()
499 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break; in insertSelect()
500 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break; in insertSelect()
501 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break; in insertSelect()
502 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break; in insertSelect()
503 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break; in insertSelect()
504 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break; in insertSelect()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 411 unsigned SubIdx = (IsI64 ? Mips::sub_32 : Mips::sub_fpeven); in expandCvtFPInt() local
417 TmpReg = getRegisterInfo().getSubReg(DstReg, SubIdx); in expandCvtFPInt()
420 DstReg = getRegisterInfo().getSubReg(DstReg, SubIdx); in expandCvtFPInt()
435 unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven; in expandExtractElementF64() local
436 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); in expandExtractElementF64()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 172 unsigned &SubIdx) const;
191 unsigned DestReg, unsigned SubIdx,
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