| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCTargetDesc.cpp | 40 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) { in ParseARMTriple() argument
41 Triple triple(TT); in ParseARMTriple()
45 unsigned Len = TT.size(); in ParseARMTriple()
50 if (Len >= 5 && TT.substr(0, 4) == "armv") in ParseARMTriple()
52 else if (Len >= 6 && TT.substr(0, 5) == "thumb") { in ParseARMTriple()
54 if (Len >= 7 && TT[5] == 'v') in ParseARMTriple()
61 unsigned SubVer = TT[Idx]; in ParseARMTriple()
66 if (Len >= Idx+2 && TT[Idx+1] == 'm') { in ParseARMTriple()
74 } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') { in ParseARMTriple()
82 } else if (Len >= Idx+2 && TT[Idx+1] == 's') { in ParseARMTriple()
[all …]
|
| /external/tcpdump/tests/ |
| D | print-A.new | 73 Configuration files can be found in <TT>/etc/apache</TT>.</LI>
76 The <TT>DocumentRoot</TT>, which is the directory under which all your
77 HTML files should exist, is set to <TT>/var/www</TT>.</LI>
80 CGI scripts are looked for in <TT>/usr/lib/cgi-bin</TT>, which is where
84 Log files are placed in <TT>/var/log/apache</TT>, and will be rotated
86 <TT>/etc/logrotate.d/apache</TT>.</LI>
89 The default directory index is <TT>index.html</TT>, meaning that requests
90 for a directory <TT>/foo/bar/</TT> will give the contents of the file <TT>/var/www/foo/bar/index.ht…
91 if it exists (assuming that <TT>/var/www</TT> is your <TT>DocumentRoot</TT>).</LI>
95 in the <TT>public_html</TT> directory of the users' homes. These dirs
[all …]
|
| D | print-AA.new | 73 Configuration files can be found in <TT>/etc/apache</TT>.</LI>
76 The <TT>DocumentRoot</TT>, which is the directory under which all your
77 HTML files should exist, is set to <TT>/var/www</TT>.</LI>
80 CGI scripts are looked for in <TT>/usr/lib/cgi-bin</TT>, which is where
84 Log files are placed in <TT>/var/log/apache</TT>, and will be rotated
86 <TT>/etc/logrotate.d/apache</TT>.</LI>
89 The default directory index is <TT>index.html</TT>, meaning that requests
90 for a directory <TT>/foo/bar/</TT> will give the contents of the file <TT>/var/www/foo/bar/index.ht…
91 if it exists (assuming that <TT>/var/www</TT> is your <TT>DocumentRoot</TT>).</LI>
95 in the <TT>public_html</TT> directory of the users' homes. These dirs
[all …]
|
| D | print-A.out | 73 Configuration files can be found in <TT>/etc/apache</TT>.</LI>
76 The <TT>DocumentRoot</TT>, which is the directory under which all your
77 HTML files should exist, is set to <TT>/var/www</TT>.</LI>
80 CGI scripts are looked for in <TT>/usr/lib/cgi-bin</TT>, which is where
84 Log files are placed in <TT>/var/log/apache</TT>, and will be rotated
86 <TT>/etc/logrotate.d/apache</TT>.</LI>
89 The default directory index is <TT>index.html</TT>, meaning that requests
90 for a directory <TT>/foo/bar/</TT> will give the contents of the file <TT>/var/www/foo/bar/index.ht…
91 if it exists (assuming that <TT>/var/www</TT> is your <TT>DocumentRoot</TT>).</LI>
95 in the <TT>public_html</TT> directory of the users' homes. These dirs
[all …]
|
| D | print-AA.out | 73 Configuration files can be found in <TT>/etc/apache</TT>.</LI>
76 The <TT>DocumentRoot</TT>, which is the directory under which all your
77 HTML files should exist, is set to <TT>/var/www</TT>.</LI>
80 CGI scripts are looked for in <TT>/usr/lib/cgi-bin</TT>, which is where
84 Log files are placed in <TT>/var/log/apache</TT>, and will be rotated
86 <TT>/etc/logrotate.d/apache</TT>.</LI>
89 The default directory index is <TT>index.html</TT>, meaning that requests
90 for a directory <TT>/foo/bar/</TT> will give the contents of the file <TT>/var/www/foo/bar/index.ht…
91 if it exists (assuming that <TT>/var/www</TT> is your <TT>DocumentRoot</TT>).</LI>
95 in the <TT>public_html</TT> directory of the users' homes. These dirs
[all …]
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCTargetDesc.cpp | 38 static std::string ParseMipsTriple(StringRef TT, StringRef CPU) { in ParseMipsTriple() argument
44 DashPosition = TT.find('-'); in ParseMipsTriple()
48 TheTriple = TT.substr(0); in ParseMipsTriple()
51 TheTriple = TT.substr(0,DashPosition); in ParseMipsTriple()
76 static MCRegisterInfo *createMipsMCRegisterInfo(StringRef TT) { in createMipsMCRegisterInfo() argument
82 static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU, in createMipsMCSubtargetInfo() argument
84 std::string ArchFS = ParseMipsTriple(TT,CPU); in createMipsMCSubtargetInfo()
92 InitMipsMCSubtargetInfo(X, TT, CPU, ArchFS); in createMipsMCSubtargetInfo()
96 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { in createMipsMCAsmInfo() argument
97 MCAsmInfo *MAI = new MipsMCAsmInfo(TT); in createMipsMCAsmInfo()
[all …]
|
| D | MipsAsmBackend.cpp | 256 MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, StringRef TT, in createMipsAsmBackendEL32() argument
258 return new MipsAsmBackend(T, Triple(TT).getOS(), in createMipsAsmBackendEL32()
262 MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, StringRef TT, in createMipsAsmBackendEB32() argument
264 return new MipsAsmBackend(T, Triple(TT).getOS(), in createMipsAsmBackendEB32()
268 MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, StringRef TT, in createMipsAsmBackendEL64() argument
270 return new MipsAsmBackend(T, Triple(TT).getOS(), in createMipsAsmBackendEL64()
274 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, StringRef TT, in createMipsAsmBackendEB64() argument
276 return new MipsAsmBackend(T, Triple(TT).getOS(), in createMipsAsmBackendEB64()
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 46 std::string X86_MC::ParseX86Triple(StringRef TT) { in ParseX86Triple() argument
47 Triple TheTriple(TT); in ParseX86Triple()
198 unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) { in getDwarfRegFlavour() argument
199 Triple TheTriple(TT); in getDwarfRegFlavour()
220 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU, in createX86MCSubtargetInfo() argument
222 std::string ArchFS = X86_MC::ParseX86Triple(TT); in createX86MCSubtargetInfo()
241 InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS); in createX86MCSubtargetInfo()
251 static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) { in createX86MCRegisterInfo() argument
252 Triple TheTriple(TT); in createX86MCRegisterInfo()
259 X86_MC::getDwarfRegFlavour(TT, false), in createX86MCRegisterInfo()
[all …]
|
| D | X86MCTargetDesc.h | 52 std::string ParseX86Triple(StringRef TT);
66 unsigned getDwarfRegFlavour(StringRef TT, bool isEH);
73 MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
82 MCAsmBackend *createX86_32AsmBackend(const Target &T, StringRef TT, StringRef CPU);
83 MCAsmBackend *createX86_64AsmBackend(const Target &T, StringRef TT, StringRef CPU);
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCTargetDesc.cpp | 43 static MCRegisterInfo *createPPCMCRegisterInfo(StringRef TT) { in createPPCMCRegisterInfo() argument
44 Triple TheTriple(TT); in createPPCMCRegisterInfo()
55 static MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU, in createPPCMCSubtargetInfo() argument
58 InitPPCMCSubtargetInfo(X, TT, CPU, FS); in createPPCMCSubtargetInfo()
62 static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { in createPPCMCAsmInfo() argument
63 Triple TheTriple(TT); in createPPCMCAsmInfo()
82 static MCCodeGenInfo *createPPCMCCodeGenInfo(StringRef TT, Reloc::Model RM, in createPPCMCCodeGenInfo() argument
88 Triple T(TT); in createPPCMCCodeGenInfo()
95 Triple T(TT); in createPPCMCCodeGenInfo()
105 static MCStreamer *createMCStreamer(const Target &T, StringRef TT, in createMCStreamer() argument
[all …]
|
| /external/clang/test/SemaTemplate/ |
| D | issue150.cpp | 44 template<typename T, typename U = T *, typename V = U const> class TT>
46 typedef TT<Z> type;
57 template<typename T, typename U = T *, typename V = U const> class TT>
59 typedef TT<Z> type;
63 template<typename T, typename U = T *, typename V = U const> class TT>
64 struct X<int, Z, TT> {
65 typedef TT<Z> type;
|
| D | deduction.cpp | 60 template<template<typename> class TT, typename T1, typename Arg1, typename Arg2>
61 struct Replace<TT<T1>, Arg1, Arg2> {
62 typedef TT<typename Replace<T1, Arg1, Arg2>::type> type;
65 template<template<typename, typename> class TT, typename T1, typename T2,
67 struct Replace<TT<T1, T2>, Arg1, Arg2> {
68 typedef TT<typename Replace<T1, Arg1, Arg2>::type,
73 template<template<typename, typename> class TT, typename T1,
75 struct Replace<TT<T1, _2>, Arg1, Arg2> {
76 typedef TT<typename Replace<T1, Arg1, Arg2>::type, Arg2> type;
|
| D | temp_class_spec_neg.cpp | 30 template<typename T, int N, template<typename X> class TT>
34 template<typename T, int N, template<typename X> class TT>
35 struct Test0<T, N, TT>; // expected-error{{does not specialize}}
40 template<typename X> class TT = ::vector> // expected-error{{default template argument}}
41 struct Test0<T*, N, TT> { };
|
| D | instantiate-template-template-parm.cpp | 34 template<template<int V> class TT> // expected-note{{parameter with type 'int'}}
37 template<typename T, template<T V> class TT>
39 X1<TT> x1; // expected-error{{has different template parameters}}
48 template <typename T, template <T, T> class TT, class R = TT<1, 2> >
64 template<template<int> class TT> struct X0
|
| D | dependent-base-classes.cpp | 21 template <class TT>
23 typedef typename A<TT>::type type;
26 template <class TT>
27 struct FI : II<TT>
32 template <class TT>
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcTargetMachine.cpp | 28 SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, in SparcTargetMachine() argument
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), in SparcTargetMachine()
35 Subtarget(TT, CPU, FS, is64bit), in SparcTargetMachine()
79 StringRef TT, StringRef CPU, in SparcV8TargetMachine() argument
85 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { in SparcV8TargetMachine()
91 StringRef TT, StringRef CPU, in SparcV9TargetMachine() argument
97 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { in SparcV9TargetMachine()
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCTargetDesc.cpp | 43 static MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT) { in createHexagonMCRegisterInfo() argument
49 static MCSubtargetInfo *createHexagonMCSubtargetInfo(StringRef TT, in createHexagonMCSubtargetInfo() argument
53 InitHexagonMCSubtargetInfo(X, TT, CPU, FS); in createHexagonMCSubtargetInfo()
58 StringRef TT) { in createHexagonMCAsmInfo() argument
59 MCAsmInfo *MAI = new HexagonMCAsmInfo(TT); in createHexagonMCAsmInfo()
69 static MCCodeGenInfo *createHexagonMCCodeGenInfo(StringRef TT, Reloc::Model RM, in createHexagonMCCodeGenInfo() argument
|
| /external/llvm/lib/Target/XCore/MCTargetDesc/ |
| D | XCoreMCTargetDesc.cpp | 41 static MCRegisterInfo *createXCoreMCRegisterInfo(StringRef TT) { in createXCoreMCRegisterInfo() argument
47 static MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU, in createXCoreMCSubtargetInfo() argument
50 InitXCoreMCSubtargetInfo(X, TT, CPU, FS); in createXCoreMCSubtargetInfo()
55 StringRef TT) { in createXCoreMCAsmInfo() argument
56 MCAsmInfo *MAI = new XCoreMCAsmInfo(TT); in createXCoreMCAsmInfo()
65 static MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM, in createXCoreMCCodeGenInfo() argument
|
| /external/llvm/include/llvm/Support/ |
| D | TargetRegistry.h | 62 MCRelocationInfo *createMCRelocationInfo(StringRef TT, MCContext &Ctx);
64 MCSymbolizer *createMCSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo,
82 typedef unsigned (*TripleMatchQualityFnTy)(const std::string &TT);
85 StringRef TT);
86 typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT,
92 typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT);
93 typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT,
97 StringRef TT,
107 StringRef TT,
124 StringRef TT,
[all …]
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXTargetMachine.cpp | 70 const Target &T, StringRef TT, StringRef CPU, StringRef FS, in NVPTXTargetMachine() argument
73 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), in NVPTXTargetMachine()
74 Subtarget(TT, CPU, FS, is64bit), DL(Subtarget.getDataLayout()), in NVPTXTargetMachine()
84 const Target &T, StringRef TT, StringRef CPU, StringRef FS, in NVPTXTargetMachine32() argument
87 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} in NVPTXTargetMachine32()
92 const Target &T, StringRef TT, StringRef CPU, StringRef FS, in NVPTXTargetMachine64() argument
95 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} in NVPTXTargetMachine64()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCTargetMachine.cpp | 36 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, in PPCTargetMachine() argument
42 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), in PPCTargetMachine()
43 Subtarget(TT, CPU, FS, is64Bit), in PPCTargetMachine()
57 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, in PPC32TargetMachine() argument
62 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { in PPC32TargetMachine()
67 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT, in PPC64TargetMachine() argument
72 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { in PPC64TargetMachine()
|
| /external/clang/test/CodeGenCXX/ |
| D | temp-order.cpp | 21 TempTracker &TT; member
26 : TT(_TT), P(_P), Truth(_Truth) {} in A()
27 A(const A &RHS) : TT(RHS.TT), P(RHS.P), Truth(RHS.Truth) { RHS.P = 0; } in A()
30 TT.Product *= pow(P, ++TT.Index); in ~A()
34 TT = RHS.TT; in operator =()
|
| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| D | SparcMCTargetDesc.cpp | 40 static MCRegisterInfo *createSparcMCRegisterInfo(StringRef TT) { in createSparcMCRegisterInfo() argument
46 static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU, in createSparcMCSubtargetInfo() argument
49 InitSparcMCSubtargetInfo(X, TT, CPU, FS); in createSparcMCSubtargetInfo()
64 static MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM, in createSparcMCCodeGenInfo() argument
77 static MCCodeGenInfo *createSparcV9MCCodeGenInfo(StringRef TT, Reloc::Model RM, in createSparcV9MCCodeGenInfo() argument
|
| /external/clang/test/CXX/temp/temp.decls/temp.alias/ |
| D | p2.cpp | 30 template<template<class> class TT>
31 void f(TT<int>); // expected-note {{candidate template ignored}}
33 template<template<class,class> class TT>
34 void g(TT<int, Alloc<int>>);
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCTargetDesc.cpp | 39 MCSubtargetInfo *AArch64_MC::createAArch64MCSubtargetInfo(StringRef TT, in createAArch64MCSubtargetInfo() argument
43 InitAArch64MCSubtargetInfo(X, TT, CPU, FS); in createAArch64MCSubtargetInfo()
61 StringRef TT) { in createAArch64MCAsmInfo() argument
62 Triple TheTriple(TT); in createAArch64MCAsmInfo()
72 static MCCodeGenInfo *createAArch64MCCodeGenInfo(StringRef TT, Reloc::Model RM, in createAArch64MCCodeGenInfo() argument
96 static MCStreamer *createMCStreamer(const Target &T, StringRef TT, in createMCStreamer() argument
102 Triple TheTriple(TT); in createMCStreamer()
|