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Searched refs:isRegLoc (Results 1 – 14 of 14) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DCallingConvLower.h117 bool isRegLoc() const { return !isMem; } in isRegLoc() function
122 unsigned getLocReg() const { assert(isRegLoc()); return Loc; } in getLocReg()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp199 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_32()
262 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_64()
364 if (VA.isRegLoc()) { in LowerFormalArguments_32()
551 if (VA.isRegLoc()) { in LowerFormalArguments_64()
788 if (VA.isRegLoc()) { in LowerCall_32()
792 if (NextVA.isRegLoc()) { in LowerCall_32()
825 if (VA.isRegLoc()) { in LowerCall_32()
950 if (!VA.isRegLoc() || VA.getLocVT() != MVT::f64) in fixupVariableFloatArgs()
1045 if (VA.isRegLoc()) { in LowerCall_64()
1054 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() && in LowerCall_64()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp1927 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1933 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) in ProcessCallArgs()
2007 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
2019 assert(VA.isRegLoc() && NextVA.isRegLoc() && in ProcessCallArgs()
2135 if (!VA.isRegLoc()) in SelectRet()
DARMISelLowering.cpp1379 if (NextVA.isRegLoc()) in PassF64ArgInRegs()
1496 if (VA.isRegLoc()) { in LowerCall()
1509 } else if (VA.isRegLoc()) { in LowerCall()
1977 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) in IsEligibleForTailCallOptimization()
1981 if (RVLocs1[i].isRegLoc()) { in IsEligibleForTailCallOptimization()
2031 if (!VA.isRegLoc()) in IsEligibleForTailCallOptimization()
2033 if (!ArgLocs[++i].isRegLoc()) in IsEligibleForTailCallOptimization()
2036 if (!ArgLocs[++i].isRegLoc()) in IsEligibleForTailCallOptimization()
2038 if (!ArgLocs[++i].isRegLoc()) in IsEligibleForTailCallOptimization()
2041 } else if (!VA.isRegLoc()) { in IsEligibleForTailCallOptimization()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp984 } else if (VA.isRegLoc()) { in LowerFormalArguments()
1094 assert(VA.isRegLoc() && "Only register-returns should be created by PCS"); in LowerReturn()
1253 if (VA.isRegLoc()) { in LowerCall()
1415 assert(VA.isRegLoc() && "Memory locations not expected for call return"); in LowerCallResult()
1501 if (!ArgLocs[i].isRegLoc()) in IsEligibleForTailCallOptimization()
1521 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) in IsEligibleForTailCallOptimization()
1525 if (RVLocs1[i].isRegLoc()) { in IsEligibleForTailCallOptimization()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp338 if (VA.isRegLoc()) { in LowerCCCArguments()
434 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
511 if (VA.isRegLoc()) { in LowerCCCCallTo()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp502 if (VA.isRegLoc()) { in LowerCall()
850 if ( (VA.isRegLoc() && !Flags.isByVal()) in LowerFormalArguments()
851 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) { in LowerFormalArguments()
870 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) { in LowerFormalArguments()
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp933 if (VA.isRegLoc()) { in LowerCCCCallTo()
1106 if (VA.isRegLoc()) { in LowerCCCArguments()
1269 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp598 if (VA.isRegLoc()) { in LowerFormalArguments()
742 if (VA.isRegLoc()) in LowerCall()
864 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp2411 if (VA.isRegLoc()) { in LowerCall()
2444 if (VA.isRegLoc()) { in LowerCall()
2602 bool IsRegLoc = VA.isRegLoc(); in LowerFormalArguments()
2756 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
/external/llvm/lib/Target/R600/
DSIISelLowering.cpp224 assert(VA.isRegLoc() && "Parameter must be in a register!"); in LowerFormalArguments()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp779 if (!VA.isRegLoc()) in X86SelectRet()
2060 if (VA.isRegLoc()) { in DoSelectCall()
DX86ISelLowering.cpp1794 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
2179 if (VA.isRegLoc()) { in LowerFormalArguments()
2605 if (VA.isRegLoc()) { in LowerCall()
2697 if (VA.isRegLoc()) in LowerCall()
3088 if (!ArgLocs[i].isRegLoc()) in IsEligibleForTailCallOptimization()
3130 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) in IsEligibleForTailCallOptimization()
3134 if (RVLocs1[i].isRegLoc()) { in IsEligibleForTailCallOptimization()
3175 if (!VA.isRegLoc()) { in IsEligibleForTailCallOptimization()
3200 if (!VA.isRegLoc()) in IsEligibleForTailCallOptimization()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp1984 if (VA.isRegLoc()) { in LowerFormalArguments_32SVR4()
3349 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerCallResult()
3667 if (VA.isRegLoc()) { in LowerCall_32SVR4()
4495 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()