| /external/llvm/lib/Target/X86/ |
| D | X86InstrAVX512.td | 4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
138 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
151 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
165 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
178 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
[all …]
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| D | X86CallingConv.td | 55 CCIfType<[v16i32, v8i64, v16f32, v8f64],
109 CCIfType<[v16f32, v8f64, v16i32, v8i64],
231 CCIfNotVarArg<CCIfType<[v16i32, v8i64, v16f32, v8f64],
251 CCIfType<[v16i32, v8i64, v16f32, v8f64],
274 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
495 CCIfType<[v16f32, v8f64, v16i32, v8i64],
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| D | X86RegisterInfo.td | 452 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v16i32, v8i64], 512,
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| D | X86ISelLowering.cpp | 1302 addRegisterClass(MVT::v16f32, &X86::VR512RegClass); in resetOperationActions()
1310 setOperationAction(ISD::LOAD, MVT::v16f32, Legal); in resetOperationActions()
1316 setOperationAction(ISD::FADD, MVT::v16f32, Legal); in resetOperationActions()
1317 setOperationAction(ISD::FSUB, MVT::v16f32, Legal); in resetOperationActions()
1318 setOperationAction(ISD::FMUL, MVT::v16f32, Legal); in resetOperationActions()
1319 setOperationAction(ISD::FDIV, MVT::v16f32, Legal); in resetOperationActions()
1320 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal); in resetOperationActions()
1321 setOperationAction(ISD::FNEG, MVT::v16f32, Custom); in resetOperationActions()
1330 setOperationAction(ISD::FMA, MVT::v16f32, Legal); in resetOperationActions()
1358 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom); in resetOperationActions()
[all …]
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| /external/llvm/test/CodeGen/X86/ |
| D | wide-fma-contraction.ll | 25 …%ret = tail call <16 x float> @llvm.fmuladd.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> …
29 declare <16 x float> @llvm.fmuladd.v16f32(<16 x float>, <16 x float>, <16 x float>) nounwind readno…
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| /external/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.h | 100 v16f32 = 45, // 16 x f32 enumerator
225 return (SimpleTy == MVT::v8f64 || SimpleTy == MVT::v16f32 || in is512BitVector()
294 case v16f32: return f32; in getVectorElementType()
315 case v16f32: return 16; in getVectorNumElements()
405 case v16f32: in getSizeInBits()
529 if (NumElements == 16) return MVT::v16f32; in getVectorVT()
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| D | ValueTypes.td | 69 def v16f32 : ValueType<512, 45>; // 16 x f32 vector value
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| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 254 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
255 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
256 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
257 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
281 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost()
282 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 } in getCastInstrCost()
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 163 case MVT::v16f32: return "v16f32"; in getEVTString()
226 case MVT::v16f32: return VectorType::get(Type::getFloatTy(Context), 16); in getTypeForEVT()
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| /external/llvm/lib/Target/R600/ |
| D | SIRegisterInfo.td | 179 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>;
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| D | SIISelLowering.cpp | 61 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass); in SITargetLowering()
68 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand); in SITargetLowering()
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| D | SIInstructions.td | 1466 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1469 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1481 def : Vector16_Build <v16f32, f32>;
1821 defm : SI_INDIRECT_Pattern <v16f32, SI_INDIRECT_DST_V16>;
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 104 case MVT::v16f32: return "MVT::v16f32"; in getEnumName()
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 171 def llvm_v16f32_ty : LLVMType<v16f32>; // 16 x float
|