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Searched refs:v8i32 (Results 1 – 22 of 22) sorted by relevance

/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp183 { ISD::SHL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
184 { ISD::SRL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
185 { ISD::SRA, MVT::v8i32, 1 }, in getArithmeticInstrCost()
204 { ISD::SDIV, MVT::v8i32, 8*20 }, in getArithmeticInstrCost()
208 { ISD::UDIV, MVT::v8i32, 8*20 }, in getArithmeticInstrCost()
300 { ISD::MUL, MVT::v8i32, 4 }, in getArithmeticInstrCost()
301 { ISD::SUB, MVT::v8i32, 4 }, in getArithmeticInstrCost()
302 { ISD::ADD, MVT::v8i32, 4 }, in getArithmeticInstrCost()
405 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, in getCastInstrCost()
406 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, in getCastInstrCost()
[all …]
DX86InstrAVX512.td52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
[all …]
DX86InstrSSE.td257 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
258 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
280 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
339 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
343 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
349 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
356 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
358 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
359 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
360 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
[all …]
DX86CallingConv.td49 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
105 CCIfType<[v8f32, v4f64, v8i32, v4i64],
225 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
247 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
271 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
369 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
377 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
491 CCIfType<[v8f32, v4f64, v8i32, v4i64],
DX86ISelLowering.cpp1118 addRegisterClass(MVT::v8i32, &X86::VR256RegClass); in resetOperationActions()
1158 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); in resetOperationActions()
1160 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); in resetOperationActions()
1163 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom); in resetOperationActions()
1182 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); in resetOperationActions()
1191 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); in resetOperationActions()
1195 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom); in resetOperationActions()
1197 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom); in resetOperationActions()
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom); in resetOperationActions()
1212 setOperationAction(ISD::ADD, MVT::v8i32, Legal); in resetOperationActions()
[all …]
DX86RegisterInfo.td438 def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
463 def VR256X : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
DX86InstrFragmentsSIMD.td391 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
/external/llvm/include/llvm/CodeGen/
DValueTypes.h85 v8i32 = 34, // 8 x i32 enumerator
220 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64); in is256BitVector()
283 case v8i32: in getVectorElementType()
319 case v8i32: in getVectorNumElements()
397 case v8i32: in getSizeInBits()
512 if (NumElements == 8) return MVT::v8i32; in getVectorVT()
DValueTypes.td57 def v8i32 : ValueType<256, 34>; // 8 x i32 vector value
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp221 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
222 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
232 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
252 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
253 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
405 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 4*8 + 1*3 + 1*4 + 1*2 }, in getCmpSelInstrCost()
DARMISelLowering.cpp568 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom); in ARMTargetLowering()
569 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom); in ARMTargetLowering()
/external/llvm/lib/IR/
DValueTypes.cpp152 case MVT::v8i32: return "v8i32"; in getEVTString()
215 case MVT::v8i32: return VectorType::get(Type::getInt32Ty(Context), 8); in getTypeForEVT()
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp98 DecodePSHUFMask(MVT::v8i32, MI->getOperand(MI->getNumOperands()-1).getImm(), in EmitAnyX86InstComments()
196 DecodeUNPCKHMask(MVT::v8i32, ShuffleMask); in EmitAnyX86InstComments()
269 DecodeUNPCKLMask(MVT::v8i32, ShuffleMask); in EmitAnyX86InstComments()
/external/llvm/lib/Target/R600/
DSIRegisterInfo.td177 def VReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 256, (add VGPR_256)>;
DSIISelLowering.cpp57 addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass); in SITargetLowering()
65 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand); in SITargetLowering()
DSIInstructions.td1372 defm : SamplePatterns<v8i32>;
1443 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1446 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1478 def : Vector8_Build <v8i32, i32>;
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DSIISelLowering.cpp38 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass); in SITargetLowering()
DSIInstructions.td392 defm S_LOAD_DWORDX8 : SMRD_Helper <0x00000003, "S_LOAD_DWORDX8", SReg_256, v8i32>;
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp93 case MVT::v8i32: return "MVT::v8i32"; in getEnumName()
/external/mesa3d/src/gallium/drivers/radeon/
DSIISelLowering.cpp38 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass); in SITargetLowering()
DSIInstructions.td392 defm S_LOAD_DWORDX8 : SMRD_Helper <0x00000003, "S_LOAD_DWORDX8", SReg_256, v8i32>;
/external/llvm/include/llvm/IR/
DIntrinsics.td160 def llvm_v8i32_ty : LLVMType<v8i32>; // 8 x i32