| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 305 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerDynamicAlloc()
329 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in lowerDynamicAlloc()
337 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in lowerDynamicAlloc()
354 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in lowerDynamicAlloc()
362 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in lowerDynamicAlloc()
404 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
416 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
448 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
460 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
521 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRBitSpilling()
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsMachineFunction.cpp | 90 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC); in getGlobalBaseReg()
103 return Mips16SPAliasReg = MF.getRegInfo().createVirtualRegister(RC); in getMips16SPAliasReg()
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| D | Mips16FrameLowering.cpp | 182 MF.getRegInfo().setPhysRegUsed(Mips::S2); in processFunctionBeforeCalleeSavedScan()
184 MF.getRegInfo().setPhysRegUsed(Mips::S0); in processFunctionBeforeCalleeSavedScan()
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| D | MipsOptimizePICCall.cpp | 119 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg); in getRegTy()
260 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in isCallViaRegister()
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| D | MipsSEISelDAGToDAG.cpp | 131 MachineRegisterInfo &RegInfo = MF.getRegInfo(); in initGlobalBaseReg()
146 MF.getRegInfo().addLiveIn(Mips::T9_64); in initGlobalBaseReg()
174 MF.getRegInfo().addLiveIn(Mips::T9); in initGlobalBaseReg()
209 MF.getRegInfo().addLiveIn(Mips::V0); in initGlobalBaseReg()
218 MachineRegisterInfo *MRI = &MF.getRegInfo(); in processFunctionAfterISel()
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| /external/llvm/lib/CodeGen/ |
| D | VirtRegMap.cpp | 56 MRI = &mf.getRegInfo(); in runOnMachineFunction()
70 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs(); in grow()
105 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); in assignVirt2StackSlot()
210 MRI = &MF->getRegInfo(); in runOnMachineFunction()
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| D | CalcSpillWeights.cpp | 33 MachineRegisterInfo &MRI = MF.getRegInfo(); in calculateSpillWeightsAndHints()
97 MachineRegisterInfo &mri = MF.getRegInfo(); in calculateSpillWeightAndHint()
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| D | PHIEliminationUtils.cpp | 36 MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo(); in findPHICopyInsertPoint()
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| D | AllocationOrder.cpp | 36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in AllocationOrder()
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| D | PrologEpilogInserter.cpp | 116 assert(!Fn.getRegInfo().getNumVirtRegs() && "Regalloc must assign all vregs"); in runOnMachineFunction()
169 Fn.getRegInfo().clearVirtRegs(); in runOnMachineFunction()
265 if (F.getRegInfo().isPhysRegUsed(Reg) || F.getMMI().callsUnwindInit()) { in calculateCalleeSavedRegisters()
883 const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(Reg); in scavengeFrameVirtualRegs()
891 Fn.getRegInfo().replaceRegWith(Reg, ScratchReg); in scavengeFrameVirtualRegs()
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| D | MachineInstr.cpp | 57 MachineRegisterInfo &MRI = MF->getRegInfo(); in setReg()
99 MachineRegisterInfo &MRI = MF->getRegInfo(); in setIsDef()
119 MF->getRegInfo().removeRegOperandFromUseList(this); in ChangeToImmediate()
135 RegInfo = &MF->getRegInfo(); in ChangeToRegister()
586 MachineRegisterInfo *MachineInstr::getRegInfo() { in getRegInfo() function in MachineInstr
588 return &MBB->getParent()->getRegInfo(); in getRegInfo()
677 MachineRegisterInfo *MRI = getRegInfo(); in addOperand()
745 MachineRegisterInfo *MRI = getRegInfo(); in RemoveOperand()
1469 MRI = &MF->getRegInfo(); in print()
1545 const MachineRegisterInfo &MRI = MF->getRegInfo(); in print()
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| D | PHIElimination.cpp | 128 MRI = &MF.getRegInfo(); in runOnMachineFunction()
260 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); in LowerPHINode()
261 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC); in LowerPHINode()
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| D | RegAllocBase.cpp | 61 MRI = &vrm.getRegInfo(); in init()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 222 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getRegAllocationHints()
269 MachineRegisterInfo *MRI = &MF.getRegInfo(); in UpdateRegAllocHint()
341 const MachineRegisterInfo *MRI = &MF.getRegInfo(); in canRealignStack()
593 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); in materializeFrameBaseRegister()
765 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); in eliminateFrameIndex()
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| /external/llvm/lib/Target/R600/ |
| D | SIFixSGPRCopies.cpp | 118 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in hasVGPROperands()
197 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction()
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| D | SIFixSGPRLiveRanges.cpp | 75 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXFrameLowering.cpp | 44 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitPrologue()
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| /external/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 297 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(), in isEAXLiveIn()
298 EE = MF.getRegInfo().livein_end(); II != EE; ++II) { in isEAXLiveIn()
344 const MachineRegisterInfo &MRI = MF.getRegInfo(); in usesTheStack()
1262 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister()); in processFunctionBeforeCalleeSavedScan()
1325 assert(!MF.getRegInfo().isLiveIn(ScratchReg) && in adjustForSegmentedStacks()
1437 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2); in adjustForSegmentedStacks()
1441 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) && in adjustForSegmentedStacks()
1478 MF.getRegInfo().setPhysRegUsed(X86::R10); in adjustForSegmentedStacks()
1479 MF.getRegInfo().setPhysRegUsed(X86::R11); in adjustForSegmentedStacks()
1627 assert(!MF.getRegInfo().isLiveIn(ScratchReg) && in adjustForHiPEPrologue()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.cpp | 295 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); in materializeFrameBaseRegister()
358 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); in eliminateFrameIndex()
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| D | AArch64CleanupLocalDynamicTLSPass.cpp | 120 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in setRegister()
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| D | AArch64StorePairSuppress.cpp | 123 MRI = &MF->getRegInfo(); in runOnMachineFunction()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcFrameLowering.cpp | 208 MachineRegisterInfo &MRI = MF.getRegInfo(); in isLeafProc()
219 MachineRegisterInfo &MRI = MF.getRegInfo(); in remapRegsForLeafProc()
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| /external/llvm/include/llvm/CodeGen/ |
| D | VirtRegMap.h | 85 MachineRegisterInfo &getRegInfo() const { return *MRI; } in getRegInfo() function
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| D | MachineFunction.h | 167 MachineRegisterInfo &getRegInfo() { return *RegInfo; }
168 const MachineRegisterInfo &getRegInfo() const { return *RegInfo; }
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIAssignInterpRegs.cpp | 90 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction()
|