/external/llvm/lib/Target/X86/InstPrinter/ |
D | X86InstComments.cpp | 31 void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, in EmitAnyX86InstComments() argument 37 switch (MI->getOpcode()) { in EmitAnyX86InstComments() 40 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments() 41 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments() 42 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments() 43 if(MI->getOperand(3).isImm()) in EmitAnyX86InstComments() 44 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask); in EmitAnyX86InstComments() 49 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments() 50 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments() 51 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments() [all …]
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D | X86ATTInstPrinter.h | 30 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot) override; 34 bool printAliasInstr(const MCInst *MI, raw_ostream &OS); 35 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, 39 void printInstruction(const MCInst *MI, raw_ostream &OS); 42 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS); 43 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS); 44 void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &OS); 45 void printAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS); 46 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &OS); 47 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &OS); [all …]
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D | X86IntelInstPrinter.h | 31 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot) override; 34 void printInstruction(const MCInst *MI, raw_ostream &O); 37 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 38 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O); 39 void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &O); 40 void printAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O); 41 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O); 42 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O); 43 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O); 44 void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O); [all …]
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/external/llvm/lib/Target/ARM/InstPrinter/ |
D | ARMInstPrinter.h | 29 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override; 33 void printInstruction(const MCInst *MI, raw_ostream &O); 37 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 39 void printSORegRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); 40 void printSORegImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); 42 void printAddrModeTBB(const MCInst *MI, unsigned OpNum, raw_ostream &O); 43 void printAddrModeTBH(const MCInst *MI, unsigned OpNum, raw_ostream &O); 44 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); 45 void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O); 46 void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum, [all …]
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D | ARMInstPrinter.cpp | 76 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument 78 unsigned Opcode = MI->getOpcode(); in printInst() 86 switch (MI->getOperand(0).getImm()) { in printInst() 99 printInstruction(MI, O); in printInst() 103 printPredicateOperand(MI, 1, O); in printInst() 112 const MCOperand &Dst = MI->getOperand(0); in printInst() 113 const MCOperand &MO1 = MI->getOperand(1); in printInst() 114 const MCOperand &MO2 = MI->getOperand(2); in printInst() 115 const MCOperand &MO3 = MI->getOperand(3); in printInst() 118 printSBitModifierOperand(MI, 6, O); in printInst() [all …]
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/external/llvm/lib/CodeGen/ |
D | ExpandPostRAPseudos.cpp | 50 bool LowerSubregToReg(MachineInstr *MI); 51 bool LowerCopy(MachineInstr *MI); 53 void TransferImplicitDefs(MachineInstr *MI); 67 ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) { in TransferImplicitDefs() argument 68 MachineBasicBlock::iterator CopyMI = MI; in TransferImplicitDefs() 71 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { in TransferImplicitDefs() 72 MachineOperand &MO = MI->getOperand(i); in TransferImplicitDefs() 79 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { in LowerSubregToReg() argument 80 MachineBasicBlock *MBB = MI->getParent(); in LowerSubregToReg() 81 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && in LowerSubregToReg() [all …]
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D | TargetInstrInfo.cpp | 63 MachineBasicBlock::iterator MI) const { in insertNoop() 121 MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI, in commuteInstruction() argument 123 const MCInstrDesc &MCID = MI->getDesc(); in commuteInstruction() 125 if (HasDef && !MI->getOperand(0).isReg()) in commuteInstruction() 129 if (!findCommutedOpIndices(MI, Idx1, Idx2)) { in commuteInstruction() 130 assert(MI->isCommutable() && "Precondition violation: MI must be commutable."); in commuteInstruction() 134 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() && in commuteInstruction() 136 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; in commuteInstruction() 137 unsigned Reg1 = MI->getOperand(Idx1).getReg(); in commuteInstruction() 138 unsigned Reg2 = MI->getOperand(Idx2).getReg(); in commuteInstruction() [all …]
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/external/llvm/lib/Target/R600/ |
D | SILowerControlFlow.cpp | 76 void SkipIfDead(MachineInstr &MI); 78 void If(MachineInstr &MI); 79 void Else(MachineInstr &MI); 80 void Break(MachineInstr &MI); 81 void IfBreak(MachineInstr &MI); 82 void ElseBreak(MachineInstr &MI); 83 void Loop(MachineInstr &MI); 84 void EndCf(MachineInstr &MI); 86 void Kill(MachineInstr &MI); 87 void Branch(MachineInstr &MI); [all …]
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/external/llvm/lib/Target/ARM/ |
D | ARMCodeEmitter.cpp | 79 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const; 87 void emitInstruction(const MachineInstr &MI); 93 void emitConstPoolInstruction(const MachineInstr &MI); 94 void emitMOVi32immInstruction(const MachineInstr &MI); 95 void emitMOVi2piecesInstruction(const MachineInstr &MI); 96 void emitLEApcrelJTInstruction(const MachineInstr &MI); 97 void emitPseudoMoveInstruction(const MachineInstr &MI); 99 void emitPseudoInstruction(const MachineInstr &MI); 100 unsigned getMachineSoRegOpValue(const MachineInstr &MI, 106 unsigned getAddrModeSBit(const MachineInstr &MI, [all …]
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D | A15SDOptimizer.cpp | 59 bool runOnInstruction(MachineInstr *MI); 99 bool hasPartialWrite(MachineInstr *MI); 100 SmallVector<unsigned, 8> getReadDPRs(MachineInstr *MI); 107 MachineInstr *elideCopies(MachineInstr *MI); 108 void elideCopiesAndPHIs(MachineInstr *MI, 114 unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg); 115 unsigned optimizeSDPattern(MachineInstr *MI); 121 void eraseInstrWithNoUses(MachineInstr *MI); 158 MachineInstr *MI = MRI->getVRegDef(SReg); in getPrefSPRLane() local 159 if (!MI) return ARM::ssub_0; in getPrefSPRLane() [all …]
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/external/llvm/lib/Target/Mips/ |
D | MipsCodeEmitter.cpp | 82 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const; 84 void emitInstruction(MachineBasicBlock::instr_iterator MI, 102 unsigned getMachineOpValue(const MachineInstr &MI, 105 unsigned getRelocation(const MachineInstr &MI, 108 unsigned getJumpTargetOpValue(const MachineInstr &MI, unsigned OpNo) const; 109 unsigned getJumpTargetOpValueMM(const MachineInstr &MI, unsigned OpNo) const; 110 unsigned getBranchTargetOpValueMM(const MachineInstr &MI, 113 unsigned getBranchTarget21OpValue(const MachineInstr &MI, 115 unsigned getBranchTarget26OpValue(const MachineInstr &MI, 117 unsigned getJumpOffset16OpValue(const MachineInstr &MI, unsigned OpNo) const; [all …]
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/external/llvm/lib/Target/Hexagon/InstPrinter/ |
D | HexagonInstPrinter.cpp | 41 void HexagonInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument 43 printInst((const HexagonMCInst*)(MI), O, Annot); in printInst() 46 void HexagonInstPrinter::printInst(const HexagonMCInst *MI, raw_ostream &O, in printInst() argument 51 if (MI->getOpcode() == Hexagon::ENDLOOP0) { in printInst() 53 assert(MI->isPacketEnd() && "Loop-end must also end the packet"); in printInst() 55 if (MI->isPacketStart()) { in printInst() 62 Nop.setPacketStart (MI->isPacketStart()); in printInst() 67 if (MI->isPacketEnd()) in printInst() 70 printInstruction(MI, O); in printInst() 74 if (MI->isPacketStart()) in printInst() [all …]
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/external/llvm/lib/Target/Mips/InstPrinter/ |
D | MipsInstPrinter.cpp | 32 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg() argument 33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg() 34 return MI.getOperand(OpNo).getReg() == R; in isReg() 79 void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument 81 switch (MI->getOpcode()) { in printInst() 91 printSaveRestore(MI, O); in printInst() 96 printSaveRestore(MI, O); in printInst() 101 printSaveRestore(MI, O); in printInst() 106 printSaveRestore(MI, O); in printInst() 112 if (!printAliasInstr(MI, O) && !printAlias(*MI, O)) in printInst() [all …]
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonRegisterInfo.cpp | 125 MachineInstr &MI = *II; in eliminateFrameIndex() local 126 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); in eliminateFrameIndex() 129 MachineFunction &MF = *MI.getParent()->getParent(); in eliminateFrameIndex() 145 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) && in eliminateFrameIndex() 146 !TII.isSpillPredRegOp(&MI)) { in eliminateFrameIndex() 148 MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister(), false, in eliminateFrameIndex() 150 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(FrameSize+Offset); in eliminateFrameIndex() 153 if (!TII.isValidOffset(MI.getOpcode(), Offset)) { in eliminateFrameIndex() 162 if ( (MI.getOpcode() == Hexagon::LDriw) || in eliminateFrameIndex() 163 (MI.getOpcode() == Hexagon::LDrid) || in eliminateFrameIndex() [all …]
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D | HexagonSplitTFRCondSets.cpp | 92 MachineInstr *MI = MII; in runOnMachineFunction() local 94 switch(MI->getOpcode()) { in runOnMachineFunction() 98 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction() 99 int SrcReg1 = MI->getOperand(2).getReg(); in runOnMachineFunction() 100 int SrcReg2 = MI->getOperand(3).getReg(); in runOnMachineFunction() 102 if (MI->getOpcode() == Hexagon::TFR_condset_rr || in runOnMachineFunction() 103 MI->getOpcode() == Hexagon::TFR_condset_rr_f) { in runOnMachineFunction() 107 else if (MI->getOpcode() == Hexagon::TFR_condset_rr64_f) { in runOnMachineFunction() 115 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc1), in runOnMachineFunction() 116 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); in runOnMachineFunction() [all …]
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D | HexagonVLIWPacketizer.cpp | 128 bool ignorePseudoInstruction(MachineInstr *MI, 133 bool isSoloInstruction(MachineInstr *MI) override; 143 MachineBasicBlock::iterator addToPacket(MachineInstr *MI) override; 145 bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg); 146 bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType, 149 bool CanPromoteToDotNew(MachineInstr* MI, SUnit* PacketSU, 154 bool CanPromoteToNewValue(MachineInstr* MI, SUnit* PacketSU, 158 bool CanPromoteToNewValueStore(MachineInstr* MI, MachineInstr* PacketMI, 161 bool DemoteToDotOld(MachineInstr* MI); 166 bool isNewifiable(MachineInstr* MI); [all …]
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D | HexagonInstrInfo.h | 50 unsigned isLoadFromStackSlot(const MachineInstr *MI, 58 unsigned isStoreToStackSlot(const MachineInstr *MI, 74 bool analyzeCompare(const MachineInstr *MI, 106 MachineInstr* MI, 111 MachineInstr* MI, in foldMemoryOperandImpl() argument 119 bool isBranch(const MachineInstr *MI) const; 120 bool isPredicable(MachineInstr *MI) const override; 121 bool PredicateInstruction(MachineInstr *MI, 134 bool isPredicated(const MachineInstr *MI) const override; 136 bool isPredicatedTrue(const MachineInstr *MI) const; [all …]
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/external/llvm/lib/Target/AArch64/InstPrinter/ |
D | AArch64InstPrinter.h | 31 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override; 35 virtual void printInstruction(const MCInst *MI, raw_ostream &O); 36 virtual bool printAliasInstr(const MCInst *MI, raw_ostream &O); 37 virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, 46 bool printSysAlias(const MCInst *MI, raw_ostream &O); 48 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 49 void printHexImm(const MCInst *MI, unsigned OpNo, raw_ostream &O); 50 void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm, 53 void printPostIncOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printPostIncOperand() argument 54 printPostIncOperand(MI, OpNo, Amount, O); in printPostIncOperand() [all …]
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/external/llvm/lib/Target/PowerPC/InstPrinter/ |
D | PPCInstPrinter.cpp | 39 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument 42 if (MI->getOpcode() == PPC::RLWINM) { in printInst() 43 unsigned char SH = MI->getOperand(2).getImm(); in printInst() 44 unsigned char MB = MI->getOperand(3).getImm(); in printInst() 45 unsigned char ME = MI->getOperand(4).getImm(); in printInst() 55 printOperand(MI, 0, O); in printInst() 57 printOperand(MI, 1, O); in printInst() 65 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) && in printInst() 66 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { in printInst() 68 printOperand(MI, 0, O); in printInst() [all …]
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZInstrInfo.cpp | 50 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI, in splitMove() argument 52 MachineBasicBlock *MBB = MI->getParent(); in splitMove() 57 MachineInstr *EarlierMI = MF.CloneMachineInstr(MI); in splitMove() 58 MBB->insert(MI, EarlierMI); in splitMove() 62 MachineOperand &LowRegOp = MI->getOperand(0); in splitMove() 69 MachineOperand &LowOffsetOp = MI->getOperand(2); in splitMove() 78 MI->setDesc(get(LowOpcode)); in splitMove() 82 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const { in splitAdjDynAlloc() 83 MachineBasicBlock *MBB = MI->getParent(); in splitAdjDynAlloc() 86 MachineOperand &OffsetMO = MI->getOperand(2); in splitAdjDynAlloc() [all …]
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
D | ARMMCCodeEmitter.cpp | 68 uint64_t getBinaryCodeForInstr(const MCInst &MI, 74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 81 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 85 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, 92 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 98 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 103 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 108 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 113 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 119 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, [all …]
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/external/llvm/lib/Target/PowerPC/ |
D | PPCCodeEmitter.cpp | 53 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const; 60 unsigned getMachineOpValue(const MachineInstr &MI, 63 unsigned get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const; 64 unsigned getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const; 65 unsigned getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const; 66 unsigned getAbsDirectBrEncoding(const MachineInstr &MI, 68 unsigned getAbsCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const; 70 unsigned getImm16Encoding(const MachineInstr &MI, unsigned OpNo) const; 71 unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const; 72 unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const; [all …]
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/external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
D | SystemZMCCodeEmitter.cpp | 38 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 44 uint64_t getBinaryCodeForInstr(const MCInst &MI, 50 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 58 uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, 61 uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, 64 uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, 67 uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, 70 uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, 78 uint64_t getPCRelEncoding(const MCInst &MI, unsigned OpNum, 82 uint64_t getPC16DBLEncoding(const MCInst &MI, unsigned OpNum, in getPC16DBLEncoding() argument [all …]
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/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
D | AArch64MCCodeEmitter.cpp | 49 uint64_t getBinaryCodeForInstr(const MCInst &MI, 55 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 63 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx, 69 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 75 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, 81 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 87 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx, 94 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx, 100 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 106 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, [all …]
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/external/llvm/lib/Target/R600/InstPrinter/ |
D | AMDGPUInstPrinter.cpp | 20 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, in printInst() argument 23 printInstruction(MI, OS); in printInst() 28 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo, in printU8ImmOperand() argument 30 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmOperand() 33 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo, in printU16ImmOperand() argument 35 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff); in printU16ImmOperand() 38 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo, in printU32ImmOperand() argument 40 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); in printU32ImmOperand() 135 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, in printOperand() argument 138 const MCOperand &Op = MI->getOperand(OpNo); in printOperand() [all …]
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