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Searched refs:MVT (Results 1 – 25 of 198) sorted by relevance

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/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp55 static const CostTblEntry<MVT::SimpleValueType> NEONFltDblTbl[] = { in getCastInstrCost()
57 { ISD::FP_ROUND, MVT::v2f64, 2 }, in getCastInstrCost()
58 { ISD::FP_EXTEND, MVT::v2f32, 2 }, in getCastInstrCost()
59 { ISD::FP_EXTEND, MVT::v4f32, 4 } in getCastInstrCost()
64 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src); in getCastInstrCost()
79 static const TypeConversionCostTblEntry<MVT::SimpleValueType> in getCastInstrCost()
81 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
82 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
83 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost()
84 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost()
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/external/llvm/include/llvm/CodeGen/
DMachineValueType.h29 class MVT {
164 LLVM_CONSTEXPR MVT() : SimpleTy(INVALID_SIMPLE_VALUE_TYPE) {} in MVT() function
165 LLVM_CONSTEXPR MVT(SimpleValueType SVT) : SimpleTy(SVT) { } in MVT() function
167 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
168 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
169 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
170 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
171 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
172 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
176 return (SimpleTy >= MVT::FIRST_VALUETYPE && in isValid()
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/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp86 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty); in getArithmeticInstrCost()
112 static const CostTblEntry<MVT::SimpleValueType> in getArithmeticInstrCost()
114 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
115 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
116 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
117 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
127 static const CostTblEntry<MVT::SimpleValueType> AVX512CostTable[] = { in getArithmeticInstrCost()
128 { ISD::SHL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
129 { ISD::SRL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
130 { ISD::SRA, MVT::v16i32, 1 }, in getArithmeticInstrCost()
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DX86ISelLowering.cpp88 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; in X86TargetLowering()
150 addRegisterClass(MVT::i8, &X86::GR8RegClass); in X86TargetLowering()
151 addRegisterClass(MVT::i16, &X86::GR16RegClass); in X86TargetLowering()
152 addRegisterClass(MVT::i32, &X86::GR32RegClass); in X86TargetLowering()
154 addRegisterClass(MVT::i64, &X86::GR64RegClass); in X86TargetLowering()
156 for (MVT VT : MVT::integer_valuetypes()) in X86TargetLowering()
157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in X86TargetLowering()
160 setTruncStoreAction(MVT::i64, MVT::i32, Expand); in X86TargetLowering()
161 setTruncStoreAction(MVT::i64, MVT::i16, Expand); in X86TargetLowering()
162 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); in X86TargetLowering()
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/external/llvm/lib/IR/
DValueTypes.cpp115 case MVT::i1: return "i1"; in getEVTString()
116 case MVT::i8: return "i8"; in getEVTString()
117 case MVT::i16: return "i16"; in getEVTString()
118 case MVT::i32: return "i32"; in getEVTString()
119 case MVT::i64: return "i64"; in getEVTString()
120 case MVT::i128: return "i128"; in getEVTString()
121 case MVT::f16: return "f16"; in getEVTString()
122 case MVT::f32: return "f32"; in getEVTString()
123 case MVT::f64: return "f64"; in getEVTString()
124 case MVT::f80: return "f80"; in getEVTString()
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/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp255 Val = CurDAG->getTargetConstant(Immed, MVT::i32); in SelectArithImmed()
256 Shift = CurDAG->getTargetConstant(ShVal, MVT::i32); in SelectArithImmed()
281 if (N.getValueType() == MVT::i32) in SelectNegArithImmed()
289 return SelectArithImmed(CurDAG->getConstant(Immed, MVT::i32), Val, Shift); in SelectNegArithImmed()
337 Shift = CurDAG->getTargetConstant(ShVal, MVT::i32); in SelectShiftedRegister()
356 if (!IsLoadStore && SrcVT == MVT::i8) in getExtendTypeForNode()
358 else if (!IsLoadStore && SrcVT == MVT::i16) in getExtendTypeForNode()
360 else if (SrcVT == MVT::i32) in getExtendTypeForNode()
362 assert(SrcVT != MVT::i64 && "extend from 64-bits?"); in getExtendTypeForNode()
368 if (!IsLoadStore && SrcVT == MVT::i8) in getExtendTypeForNode()
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DAArch64TargetTransformInfo.cpp190 static const TypeConversionCostTblEntry<MVT> ConversionTbl[] = { in getCastInstrCost()
192 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
193 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
194 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
195 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
196 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
197 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
200 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
201 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
202 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
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DAArch64ISelLowering.cpp90 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass); in AArch64TargetLowering()
91 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass); in AArch64TargetLowering()
94 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
95 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass); in AArch64TargetLowering()
96 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass); in AArch64TargetLowering()
97 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass); in AArch64TargetLowering()
101 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass); in AArch64TargetLowering()
102 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
104 addDRTypeForNEON(MVT::v2f32); in AArch64TargetLowering()
105 addDRTypeForNEON(MVT::v8i8); in AArch64TargetLowering()
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DAArch64FastISel.cpp139 bool isTypeLegal(Type *Ty, MVT &VT);
140 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
144 bool simplifyAddress(Address &Addr, MVT VT);
153 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
158 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
161 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
164 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
167 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
172 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
181 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
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/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp65 CC_Hexagon(unsigned ValNo, MVT ValVT,
66 MVT LocVT, CCValAssign::LocInfo LocInfo,
70 CC_Hexagon32(unsigned ValNo, MVT ValVT,
71 MVT LocVT, CCValAssign::LocInfo LocInfo,
75 CC_Hexagon64(unsigned ValNo, MVT ValVT,
76 MVT LocVT, CCValAssign::LocInfo LocInfo,
80 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
81 MVT LocVT, CCValAssign::LocInfo LocInfo,
85 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
86 MVT LocVT, CCValAssign::LocInfo LocInfo,
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DHexagonISelDAGToDAG.cpp112 return CurDAG->getTargetConstant(bitPos, MVT::i32); in XformMskToBitPosU5Imm()
138 return CurDAG->getTargetConstant( - Imm, MVT::i32); in XformM5ToU5Imm()
145 return CurDAG->getTargetConstant(Imm - 1, MVT::i8); in XformU7ToU7M1Imm()
150 return CurDAG->getTargetConstant(Imm - 1, MVT::i32); in XformSToSM1Imm()
156 return CurDAG->getTargetConstant(Imm - 1, MVT::i32); in XformUToUM1Imm()
161 return CurDAG->getTargetConstant(Imm - 2, MVT::i32); in XformSToSM2Imm()
166 return CurDAG->getTargetConstant(Imm - 3, MVT::i32); in XformSToSM3Imm()
258 SDValue TargetConst = CurDAG->getTargetConstant(Val, MVT::i32); in SelectIndexedLoadSignExtend64()
259 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32, in SelectIndexedLoadSignExtend64()
260 MVT::Other, Base, TargetConst, in SelectIndexedLoadSignExtend64()
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/external/llvm/utils/TableGen/
DCodeGenTarget.cpp38 MVT::SimpleValueType llvm::getValueType(Record *Rec) { in getValueType()
39 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); in getValueType()
42 std::string llvm::getName(MVT::SimpleValueType T) { in getName()
44 case MVT::Other: return "UNKNOWN"; in getName()
45 case MVT::iPTR: return "TLI.getPointerTy()"; in getName()
46 case MVT::iPTRAny: return "TLI.getPointerTy()"; in getName()
51 std::string llvm::getEnumName(MVT::SimpleValueType T) { in getEnumName()
53 case MVT::Other: return "MVT::Other"; in getEnumName()
54 case MVT::i1: return "MVT::i1"; in getEnumName()
55 case MVT::i8: return "MVT::i8"; in getEnumName()
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/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp51 (int)MVT::i8, in InitAMDILLowering()
52 (int)MVT::i16, in InitAMDILLowering()
53 (int)MVT::i32, in InitAMDILLowering()
54 (int)MVT::f32, in InitAMDILLowering()
55 (int)MVT::f64, in InitAMDILLowering()
56 (int)MVT::i64, in InitAMDILLowering()
57 (int)MVT::v2i8, in InitAMDILLowering()
58 (int)MVT::v4i8, in InitAMDILLowering()
59 (int)MVT::v2i16, in InitAMDILLowering()
60 (int)MVT::v4i16, in InitAMDILLowering()
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/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp436 if (OpVT == MVT::f16) { in getFPEXT()
437 if (RetVT == MVT::f32) in getFPEXT()
439 } else if (OpVT == MVT::f32) { in getFPEXT()
440 if (RetVT == MVT::f64) in getFPEXT()
442 if (RetVT == MVT::f128) in getFPEXT()
444 } else if (OpVT == MVT::f64) { in getFPEXT()
445 if (RetVT == MVT::f128) in getFPEXT()
455 if (RetVT == MVT::f16) { in getFPROUND()
456 if (OpVT == MVT::f32) in getFPROUND()
458 if (OpVT == MVT::f64) in getFPROUND()
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/external/llvm/lib/Target/R600/
DSIISelLowering.cpp41 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass); in SITargetLowering()
42 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass); in SITargetLowering()
44 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass); in SITargetLowering()
45 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass); in SITargetLowering()
47 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass); in SITargetLowering()
48 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass); in SITargetLowering()
50 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass); in SITargetLowering()
51 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass); in SITargetLowering()
52 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass); in SITargetLowering()
54 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass); in SITargetLowering()
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DAMDGPUISelLowering.cpp74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT, in allocateStack()
93 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32); in getEquivalentMemType()
102 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32); in getEquivalentLoadRegType()
108 setOperationAction(ISD::Constant, MVT::i32, Legal); in AMDGPUTargetLowering()
109 setOperationAction(ISD::Constant, MVT::i64, Legal); in AMDGPUTargetLowering()
110 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); in AMDGPUTargetLowering()
111 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); in AMDGPUTargetLowering()
113 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in AMDGPUTargetLowering()
114 setOperationAction(ISD::BRIND, MVT::Other, Expand); in AMDGPUTargetLowering()
117 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in AMDGPUTargetLowering()
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DAMDGPUISelDAGToDAG.cpp193 return CurDAG->getTargetConstant(Imm, MVT::i32); in getSmallIPtrImm()
201 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); in SelectADDRParam()
202 R2 = CurDAG->getTargetConstant(0, MVT::i32); in SelectADDRParam()
205 R2 = CurDAG->getTargetConstant(0, MVT::i32); in SelectADDRParam()
212 R2 = CurDAG->getTargetConstant(0, MVT::i32); in SelectADDRParam()
234 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64); in SelectADDR64()
235 R2 = CurDAG->getTargetConstant(0, MVT::i64); in SelectADDR64()
238 R2 = CurDAG->getTargetConstant(0, MVT::i64); in SelectADDR64()
245 R2 = CurDAG->getTargetConstant(0, MVT::i64); in SelectADDR64()
264 if (N->getValueType(0) != MVT::i64 || in Select()
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/external/llvm/lib/Target/X86/Utils/
DX86ShuffleDecode.h27 class MVT; variable
39 void DecodeMOVSLDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
41 void DecodeMOVSHDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
43 void DecodeMOVDDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
45 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
47 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
49 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
51 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
53 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
55 void DecodePSHUFLWMask(MVT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
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/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp113 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
145 bool isTypeLegal(Type *Ty, MVT &VT);
146 bool isLoadTypeLegal(Type *Ty, MVT &VT);
152 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
155 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
157 void PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
159 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
161 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
162 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
163 unsigned PPCMaterializeInt(const Constant *C, MVT VT, bool UseSExt = true);
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DPPCISelLowering.cpp73 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
74 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
75 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
78 for (MVT VT : MVT::integer_valuetypes()) { in PPCTargetLowering()
79 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in PPCTargetLowering()
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in PPCTargetLowering()
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
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/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.cpp561 return CurDAG->getMachineNode(NVPTX::texsurf_handles, SDLoc(N), MVT::i64, in SelectTexSurfHandle()
646 MVT SimpleVT = LoadedVT.getSimpleVT(); in SelectLoad()
664 MVT ScalarVT = SimpleVT.getScalarType(); in SelectLoad()
681 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy; in SelectLoad()
685 case MVT::i8: in SelectLoad()
688 case MVT::i16: in SelectLoad()
691 case MVT::i32: in SelectLoad()
694 case MVT::i64: in SelectLoad()
697 case MVT::f32: in SelectLoad()
700 case MVT::f64: in SelectLoad()
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DNVPTXISelLowering.cpp57 static bool IsPTXVectorType(MVT VT) { in IsPTXVectorType()
61 case MVT::v2i1: in IsPTXVectorType()
62 case MVT::v4i1: in IsPTXVectorType()
63 case MVT::v2i8: in IsPTXVectorType()
64 case MVT::v4i8: in IsPTXVectorType()
65 case MVT::v2i16: in IsPTXVectorType()
66 case MVT::v4i16: in IsPTXVectorType()
67 case MVT::v2i32: in IsPTXVectorType()
68 case MVT::v4i32: in IsPTXVectorType()
69 case MVT::v2i64: in IsPTXVectorType()
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/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp105 bool isTypeLegal(Type *Ty, MVT &VT);
106 bool isTypeSupported(Type *Ty, MVT &VT);
107 bool isLoadTypeLegal(Type *Ty, MVT &VT);
114 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
116 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
118 bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
120 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
121 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
124 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
126 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
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/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp39 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_SRet()
40 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_SRet()
52 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_f64()
53 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_f64()
81 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, in CC_Sparc64_Full()
82 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc64_Full()
84 assert((LocVT == MVT::f32 || LocVT == MVT::f128 in CC_Sparc64_Full()
89 unsigned size = (LocVT == MVT::f128) ? 16 : 8; in CC_Sparc64_Full()
90 unsigned alignment = (LocVT == MVT::f128) ? 16 : 8; in CC_Sparc64_Full()
94 if (LocVT == MVT::i64 && Offset < 6*8) in CC_Sparc64_Full()
[all …]
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp76 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass); in XCoreTargetLowering()
93 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in XCoreTargetLowering()
94 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in XCoreTargetLowering()
95 setOperationAction(ISD::ADDC, MVT::i32, Expand); in XCoreTargetLowering()
96 setOperationAction(ISD::ADDE, MVT::i32, Expand); in XCoreTargetLowering()
97 setOperationAction(ISD::SUBC, MVT::i32, Expand); in XCoreTargetLowering()
98 setOperationAction(ISD::SUBE, MVT::i32, Expand); in XCoreTargetLowering()
101 setOperationAction(ISD::ADD, MVT::i64, Custom); in XCoreTargetLowering()
102 setOperationAction(ISD::SUB, MVT::i64, Custom); in XCoreTargetLowering()
103 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); in XCoreTargetLowering()
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