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Searched refs:SDValue (Results 1 – 25 of 111) sorted by relevance

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/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypes.h86 SmallDenseMap<SDValue, SDValue, 8> PromotedIntegers;
90 SmallDenseMap<SDValue, std::pair<SDValue, SDValue>, 8> ExpandedIntegers;
94 SmallDenseMap<SDValue, SDValue, 8> SoftenedFloats;
99 SmallDenseMap<SDValue, SDValue, 8> PromotedFloats;
103 SmallDenseMap<SDValue, std::pair<SDValue, SDValue>, 8> ExpandedFloats;
107 SmallDenseMap<SDValue, SDValue, 8> ScalarizedVectors;
111 SmallDenseMap<SDValue, std::pair<SDValue, SDValue>, 8> SplitVectors;
115 SmallDenseMap<SDValue, SDValue, 8> WidenedVectors;
119 SmallDenseMap<SDValue, SDValue, 8> ReplacedValues;
143 ReplacedValues[SDValue(Old, i)] = SDValue(New, i); in NoteDeletion()
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/external/llvm/lib/Target/Mips/
DMipsSEISelDAGToDAG.h33 unsigned getMSACtrlReg(const SDValue RegIdx) const;
40 SDNode *selectAddESubE(unsigned MOp, SDValue InFlag, SDValue CmpLHS,
43 bool selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const;
44 bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset,
47 bool selectAddrRegImm(SDValue Addr, SDValue &Base,
48 SDValue &Offset) const override;
50 bool selectAddrRegReg(SDValue Addr, SDValue &Base,
51 SDValue &Offset) const override;
53 bool selectAddrDefault(SDValue Addr, SDValue &Base,
54 SDValue &Offset) const override;
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DMipsISelDAGToDAG.h57 virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base,
58 SDValue &Offset) const;
62 virtual bool selectAddrRegReg(SDValue Addr, SDValue &Base,
63 SDValue &Offset) const;
66 virtual bool selectAddrDefault(SDValue Addr, SDValue &Base,
67 SDValue &Offset) const;
70 virtual bool selectIntAddr(SDValue Addr, SDValue &Base,
71 SDValue &Offset) const;
73 virtual bool selectIntAddrMM(SDValue Addr, SDValue &Base,
74 SDValue &Offset) const;
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DMipsISelDAGToDAG.cpp68 bool MipsDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base, in selectAddrRegImm()
69 SDValue &Offset) const { in selectAddrRegImm()
74 bool MipsDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base, in selectAddrRegReg()
75 SDValue &Offset) const { in selectAddrRegReg()
80 bool MipsDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base, in selectAddrDefault()
81 SDValue &Offset) const { in selectAddrDefault()
86 bool MipsDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base, in selectIntAddr()
87 SDValue &Offset) const { in selectIntAddr()
92 bool MipsDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base, in selectIntAddrMM()
93 SDValue &Offset) const { in selectIntAddrMM()
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DMipsISelLowering.h233 SmallVectorImpl<SDValue> &Results,
237 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
242 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
252 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
269 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
276 SDValue getAddrLocal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, in getAddrLocal()
279 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), in getAddrLocal()
281 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, in getAddrLocal()
285 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, in getAddrLocal()
295 SDValue getAddrGlobal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, in getAddrGlobal()
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/external/llvm/lib/Target/R600/
DAMDGPUISelLowering.h32 SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
33 const SDValue &InitPtr,
34 SDValue Chain,
36 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
39 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
42 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
46 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
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DR600ISelLowering.h29 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
30 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
32 SmallVectorImpl<SDValue> &Results,
34 SDValue LowerFormalArguments(
35 SDValue Chain,
40 SmallVectorImpl<SDValue> &InVals) const override;
48 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
53 SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG) const;
54 SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
56 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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DSIISelLowering.h24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
25 SDValue Chain, unsigned Offset, bool Signed) const;
26 SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op,
28 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
31 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
32 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
33 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
34 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
35 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
36 SDValue LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const;
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DAMDGPUISelDAGToDAG.cpp53 inline SDValue getSmallIPtrImm(unsigned Imm);
54 bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
56 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
57 bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
60 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
61 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
62 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
83 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
84 bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
85 SDValue& Offset);
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/external/llvm/include/llvm/Target/
DTargetSelectionDAGInfo.h55 virtual SDValue
57 SDValue Chain, in EmitTargetCodeForMemcpy()
58 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemcpy()
59 SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemcpy()
63 return SDValue(); in EmitTargetCodeForMemcpy()
72 virtual SDValue
74 SDValue Chain, in EmitTargetCodeForMemmove()
75 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemmove()
76 SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove()
79 return SDValue(); in EmitTargetCodeForMemmove()
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/external/llvm/include/llvm/CodeGen/
DSelectionDAG.h187 SDValue Root;
322 const SDValue &getRoot() const { return Root; }
325 SDValue getEntryNode() const {
326 return SDValue(const_cast<SDNode *>(&EntryNode), 0);
331 const SDValue &setRoot(SDValue N) {
416 SDValue getConstant(uint64_t Val, EVT VT, bool isTarget = false,
418 SDValue getConstant(const APInt &Val, EVT VT, bool isTarget = false,
420 SDValue getConstant(const ConstantInt &Val, EVT VT, bool isTarget = false,
422 SDValue getIntPtrConstant(uint64_t Val, bool isTarget = false);
423 SDValue getTargetConstant(uint64_t Val, EVT VT, bool isOpaque = false) {
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/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.h388 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
427 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
428 SDValue &Offset,
435 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
442 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
447 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
454 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
459 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
462 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
463 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
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/external/llvm/lib/Target/XCore/
DXCoreISelLowering.h100 bool isZExtFree(SDValue Val, EVT VT2) const override;
107 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
112 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
130 SDValue LowerCCCArguments(SDValue Chain,
135 SmallVectorImpl<SDValue> &InVals) const;
136 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
140 const SmallVectorImpl<SDValue> &OutVals,
143 SmallVectorImpl<SDValue> &InVals) const;
144 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
145 SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
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/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.h232 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
252 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
256 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
283 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
302 bool isZExtFree(SDValue Val, EVT VT2) const override;
368 SDValue
369 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
372 SmallVectorImpl<SDValue> &InVals) const override;
374 SDValue LowerCall(CallLoweringInfo & /*CLI*/,
375 SmallVectorImpl<SDValue> &InVals) const override;
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/external/llvm/lib/Target/SystemZ/
DSystemZSelectionDAGInfo.h28 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
29 SDValue Dst, SDValue Src,
30 SDValue Size, unsigned Align,
35 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc DL,
36 SDValue Chain, SDValue Dst, SDValue Byte,
37 SDValue Size, unsigned Align, bool IsVolatile,
40 std::pair<SDValue, SDValue>
41 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
42 SDValue Src1, SDValue Src2, SDValue Size,
46 std::pair<SDValue, SDValue>
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DSystemZISelLowering.h246 void LowerAsmOperandForConstraint(SDValue Op,
248 std::vector<SDValue> &Ops,
273 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
276 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
280 SmallVectorImpl<SDValue> &InVals) const override;
281 SDValue LowerCall(CallLoweringInfo &CLI,
282 SmallVectorImpl<SDValue> &InVals) const override;
284 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
286 const SmallVectorImpl<SDValue> &OutVals,
288 SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
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DSystemZSelectionDAGInfo.cpp32 static SDValue emitMemMem(SelectionDAG &DAG, SDLoc DL, unsigned Sequence, in emitMemMem()
33 unsigned Loop, SDValue Chain, SDValue Dst, in emitMemMem()
34 SDValue Src, uint64_t Size) { in emitMemMem()
55 SDValue SystemZSelectionDAGInfo::
56 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain, in EmitTargetCodeForMemcpy()
57 SDValue Dst, SDValue Src, SDValue Size, unsigned Align, in EmitTargetCodeForMemcpy()
62 return SDValue(); in EmitTargetCodeForMemcpy()
67 return SDValue(); in EmitTargetCodeForMemcpy()
73 static SDValue memsetStore(SelectionDAG &DAG, SDLoc DL, SDValue Chain, in memsetStore()
74 SDValue Dst, uint64_t ByteVal, uint64_t Size, in memsetStore()
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/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUISelLowering.h27 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
28 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
35 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
38 bool isHWTrueValue(SDValue Op) const;
39 bool isHWFalseValue(SDValue Op) const;
44 virtual SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
48 SmallVectorImpl<SDValue> &InVals) const;
50 virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
53 const SmallVectorImpl<SDValue> &OutVals,
56 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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/external/llvm/lib/Target/ARM/
DARMISelLowering.h235 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
240 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
260 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
261 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
279 bool isZExtFree(SDValue Val, EVT VT2) const override;
281 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
306 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
313 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
314 SDValue &Offset, ISD::MemIndexedMode &AM,
317 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
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DARMISelDAGToDAG.cpp86 inline SDValue getI32Imm(unsigned Imm) { in getI32Imm()
94 bool isShifterOpProfitable(const SDValue &Shift,
96 bool SelectRegShifterOperand(SDValue N, SDValue &A,
97 SDValue &B, SDValue &C,
99 bool SelectImmShifterOperand(SDValue N, SDValue &A,
100 SDValue &B, bool CheckProfitability = true);
101 bool SelectShiftRegShifterOperand(SDValue N, SDValue &A, in SelectShiftRegShifterOperand()
102 SDValue &B, SDValue &C) { in SelectShiftRegShifterOperand()
106 bool SelectShiftImmShifterOperand(SDValue N, SDValue &A, in SelectShiftImmShifterOperand()
107 SDValue &B) { in SelectShiftImmShifterOperand()
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/external/llvm/lib/Target/X86/
DX86ISelLowering.h537 bool isZeroNode(SDValue Elt);
578 SDValue getPICJumpTableRelocBase(SDValue Table,
621 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
626 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
630 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
642 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
661 void computeKnownBitsForTargetNode(const SDValue Op,
668 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
675 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
693 void LowerAsmOperandForConstraint(SDValue Op,
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/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.h124 IsEligibleForTailCallOptimization(SDValue Callee,
131 const SmallVectorImpl<SDValue> &OutVals,
144 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
146 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
147 SDValue LowerEXTRACT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
148 SDValue LowerINSERT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
149 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
150 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
151 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
152 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
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DHexagonISelDAGToDAG.cpp69 inline bool SelectAddrGA(SDValue &N, SDValue &R);
70 inline bool SelectAddrGP(SDValue &N, SDValue &R);
71 bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP);
72 bool SelectAddrFI(SDValue &N, SDValue &R);
81 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
83 std::vector<SDValue> &OutOps) override;
107 SDValue XformMskToBitPosU5Imm(uint32_t Imm) { in XformMskToBitPosU5Imm()
117 SDValue XformMskToBitPosU4Imm(uint16_t Imm) { in XformMskToBitPosU4Imm()
123 SDValue XformMskToBitPosU3Imm(uint8_t Imm) { in XformMskToBitPosU3Imm()
136 inline SDValue XformM5ToU5Imm(signed Imm) { in XformM5ToU5Imm()
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/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.h78 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
84 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
85 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
92 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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/external/llvm/lib/Target/Sparc/
DSparcISelLowering.h58 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
63 void computeKnownBitsForTargetNode(const SDValue Op,
79 void LowerAsmOperandForConstraint(SDValue Op,
81 std::vector<SDValue> &Ops,
94 SDValue
95 LowerFormalArguments(SDValue Chain,
100 SmallVectorImpl<SDValue> &InVals) const override;
101 SDValue LowerFormalArguments_32(SDValue Chain,
106 SmallVectorImpl<SDValue> &InVals) const;
107 SDValue LowerFormalArguments_64(SDValue Chain,
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