| /external/blktrace/btt/ |
| D | latency.c | 23 static inline void latency_out(FILE *ofp, __u64 tstamp, __u64 latency) in latency_out() argument
26 fprintf(ofp, "%lf %lf\n", TO_SEC(tstamp), TO_SEC(latency)); in latency_out()
57 void latency_q2d(struct d_info *dip, __u64 tstamp, __u64 latency) in latency_q2d() argument
59 plat_x2c(dip->q2d_plat_handle, tstamp, latency); in latency_q2d()
60 latency_out(dip->q2d_ofp, tstamp, latency); in latency_q2d()
63 void latency_d2c(struct d_info *dip, __u64 tstamp, __u64 latency) in latency_d2c() argument
65 plat_x2c(dip->d2c_plat_handle, tstamp, latency); in latency_d2c()
66 latency_out(dip->d2c_ofp, tstamp, latency); in latency_d2c()
69 void latency_q2c(struct d_info *dip, __u64 tstamp, __u64 latency) in latency_q2c() argument
71 plat_x2c(dip->q2c_plat_handle, tstamp, latency); in latency_q2c()
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| D | plat.c | 67 void plat_x2c(void *info, __u64 ts, __u64 latency) in plat_x2c() argument
70 double lat = TO_SEC(latency); in plat_x2c()
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| D | globals.h | 241 void latency_q2d(struct d_info *dip, __u64 tstamp, __u64 latency);
242 void latency_d2c(struct d_info *dip, __u64 tstamp, __u64 latency);
243 void latency_q2c(struct d_info *dip, __u64 tstamp, __u64 latency);
281 void plat_x2c(void *info, __u64 ts, __u64 latency);
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| D | Android.mk | 5 latency.c misc.c output.c proc.c seek.c trace.c \
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| /external/iproute2/tc/ |
| D | q_tbf.c | 45 unsigned buffer=0, mtu=0, mpu=0, latency=0; in tbf_parse_opt() local
56 if (opt.limit || latency) { in tbf_parse_opt()
67 if (opt.limit || latency) { in tbf_parse_opt()
71 if (get_time(&latency, *argv)) { in tbf_parse_opt()
175 if (opt.limit == 0 && latency == 0) { in tbf_parse_opt()
181 double lim = opt.rate.rate*(double)latency/TIME_UNITS_PER_SEC + buffer; in tbf_parse_opt()
183 double lim2 = opt.peakrate.rate*(double)latency/TIME_UNITS_PER_SEC + mtu; in tbf_parse_opt()
223 double latency; in tbf_print_opt() local
266 …latency = TIME_UNITS_PER_SEC*(qopt->limit/(double)qopt->rate.rate) - tc_core_tick2time(qopt->buffe… in tbf_print_opt()
269 if (lat2 > latency) in tbf_print_opt()
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| D | q_netem.c | 200 if (get_ticks(&opt.latency, *argv)) { in netem_parse_opt()
427 if (opt.latency == 0) { in netem_parse_opt()
440 if (dist_data && (opt.latency == 0 || opt.jitter == 0)) { in netem_parse_opt()
555 if (qopt.latency) { in netem_print_opt()
556 fprintf(f, " delay %s", sprint_ticks(qopt.latency, b1)); in netem_print_opt()
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_fs_schedule_instructions.cpp | 73 this->latency = 1 * chans * math_latency; in schedule_node()
76 this->latency = 2 * chans * math_latency; in schedule_node()
82 this->latency = 3 * chans * math_latency; in schedule_node()
87 this->latency = 4 * chans * math_latency; in schedule_node()
90 this->latency = 8 * chans * math_latency; in schedule_node()
95 this->latency = 5 * chans * math_latency; in schedule_node()
98 this->latency = 2; in schedule_node()
110 int latency; member in schedule_node
129 void add_dep(schedule_node *before, schedule_node *after, int latency);
168 int latency) in add_dep() argument
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| /external/llvm/lib/Target/R600/ |
| D | SISchedule.td | 47 int latency> : WriteRes<write, resources> {
48 let Latency = latency;
51 class HWVALUWriteRes<SchedWrite write, int latency> :
52 HWWriteRes<write, [HWVALU], latency>;
55 // The latency numbers are taken from AMD Accelerated Parallel Processing
58 // The latency values are 1 / (operations / cycle) / 4.
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| /external/libvncserver/x11vnc/ |
| D | rates.c | 52 int link_rate(int *latency, int *netrate);
156 if (cd->latency == 0.0) { in get_latency()
161 lat = cd->latency; in get_latency()
282 int link_rate(int *latency, int *netrate) { in link_rate() argument
283 *latency = get_net_latency(); in link_rate()
296 if (*latency == LATENCY0 && *netrate == NETRATE0) { in link_rate()
298 } else if (*latency > 150 || *netrate < 20) { in link_rate()
300 } else if (*latency > 50 || *netrate < 150) { in link_rate()
302 } else if (*latency < 10 && *netrate > 300) { in link_rate()
694 cd->latency = dt3; in measure_send_rates()
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| D | rates.h | 50 extern int link_rate(int *latency, int *netrate);
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| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleA9.td | 435 // no delay slots, so the latency of a branch is unimportant
469 // Extra latency cycles since wbck is 2 cycles
478 // Extra latency cycles since wbck is 2 cycles
488 // Extra latency cycles since wbck is 4 cycles
497 // Extra latency cycles since wbck is 4 cycles
669 // Extra 1 latency cycle since wbck is 2 cycles
678 // Extra 1 latency cycle since wbck is 2 cycles
709 // FIXME: Result latency is 1 if address is 64-bit aligned.
881 // Extra latency cycles since wbck is 7 cycles
909 // Extra latency cycles since wbck is 7 cycles
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| /external/jmonkeyengine/engine/src/test/jme3test/network/ |
| D | TestLatency.java | 90 long latency = (curTime - timeMsg.timeSent); in main()
91 System.out.println("Latency: " + (latency) + " ms"); in main()
95 average.add(latency); in main()
98 long latencyOffset = latency - average.getAverage(); in main()
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| /external/fio/examples/ |
| D | latency-profile.fio | 1 # Test job that demonstrates how to use the latency target
3 # that fits within the latency constraints of this 4k random
13 # Set max acceptable latency to 500msec
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| /external/v8/test/perf-test/Collections/ |
| D | base.js | 44 function BenchmarkResult(benchmark, time, latency) { argument
47 this.latency = latency;
191 if (measurements[i].latency != 0) {
192 log += Math.log(measurements[i].latency);
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCScheduleA2.td | 105 [82, 0, 0]>, // L2 latency
113 [82, 0, 0]>, // L2 latency
115 [82, 0, 0]>, // L2 latency
164 let LoadLatency = 6; // Optimistic load latency assuming bypass.
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| /external/libnl/lib/route/sch/ |
| D | tbf.c | 234 static inline double calc_limit(struct rtnl_ratespec *spec, int latency, in calc_limit() argument
239 limit = (double) spec->rs_rate * ((double) latency / 1000000.); in calc_limit()
263 int rtnl_qdisc_tbf_set_limit_by_latency(struct rtnl_qdisc *qdisc, int latency) in rtnl_qdisc_tbf_set_limit_by_latency() argument
275 limit = calc_limit(&tbf->qt_rate, latency, tbf->qt_rate_bucket); in rtnl_qdisc_tbf_set_limit_by_latency()
278 limit2 = calc_limit(&tbf->qt_peakrate, latency, in rtnl_qdisc_tbf_set_limit_by_latency()
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| /external/llvm/test/CodeGen/X86/ |
| D | x86-64-double-shifts-Oz-Os-O2.ll | 5 ; even for X86_64 processors that are known to have poor latency double
27 ; even for X86_64 processors that are known to have poor latency double
48 ; for size for X86_64 processors that are known to have poor latency double
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| D | misched-copy.ll | 26 ; Do some dependent long latency stuff.
32 ; Do some independent long latency stuff.
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| /external/linux-tools-perf/src/tools/perf/Documentation/ |
| D | perf-sched.txt | 11 'perf sched' {record|latency|map|replay|script}
20 'perf sched latency' to report the per task scheduling latencies
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| /external/linux-tools-perf/src/tools/perf/scripts/perl/bin/ |
| D | wakeup-latency-report | 3 perf script $@ -s "$PERF_EXEC_PATH"/scripts/perl/wakeup-latency.pl
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 18 let LoadLatency = 4; // Optimistic load latency.
94 // Define scheduler read/write resources and latency on Cyclone.
180 // shortening its writer's latency.
229 // latency. However, general heuristics should not model the
237 // Rt latency is latency WriteIS + WriteLD.
262 // Address pre/post increment is a simple ALU op with one cycle latency.
294 // System instructions get an invalid latency because the latency of
304 // Define some longer latency vector op types for Cyclone.
547 // TODO: Add 64-bit variant with 19 cycle latency.
548 // TODO: Specialize FSQRT for longer latency.
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| /external/llvm/include/llvm/Target/ |
| D | TargetSchedule.td | 28 // processor resources and latency with each SchedReadWrite type.
85 int HighLatency = -1; // Approximation of cycles for "high latency" ops.
129 // an in-order latency resource. In this case, the scheduler models
215 // SchedWrites with additive latency. This allows a single operand to
246 // Define the resources and latency of a SchedWrite. This will be used
263 // regardless of latency, which models a fully pipelined processing
304 // to reduce latency of a prior write by N cycles. A negative advance
305 // effectively increases latency, which may be used for cross-domain
349 // latency. However, if the parent SchedWriteVariant or
352 // operands. In this case, latency is not additive. If the current Variant
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| /external/llvm/lib/Target/X86/ |
| D | X86ScheduleBtVer2.td | 21 let LoadLatency = 5; // FPU latency (worse case cf Integer 3 cycle latency)
84 // latency.
97 // latency.
155 // Branches don't produce values, so they have no latency, but they still
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| D | X86ScheduleSLM.td | 66 // latency.
91 // This is quite rough, latency depends on the dividend.
112 // This is quite rough, latency depends on precision
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| /external/okhttp/okhttp-tests/src/test/java/com/squareup/okhttp/ |
| D | DelegatingSSLSocket.java | 280 @Override public void setPerformancePreferences(int connectionTime, int latency, int bandwidth) { in setPerformancePreferences() argument
281 delegate.setPerformancePreferences(connectionTime, latency, bandwidth); in setPerformancePreferences()
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