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Searched refs:EXTRACT_VECTOR_ELT (Results 1 – 25 of 31) sorted by relevance

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/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp158 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
159 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
160 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
161 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
170 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in R600TargetLowering()
592 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
789 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
791 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
793 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
795 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
[all …]
DSIISelLowering.cpp212 case ISD::EXTRACT_VECTOR_ELT: in SITargetLowering()
234 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
235 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32); in SITargetLowering()
1257 SDValue I = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ, in LowerINTRINSIC_WO_CHAIN()
1259 SDValue J = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ, in LowerINTRINSIC_WO_CHAIN()
1394 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero); in LowerSELECT()
1395 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero); in LowerSELECT()
1399 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One); in LowerSELECT()
1400 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One); in LowerSELECT()
1537 SDValue NumHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, NumBC, Hi); in LowerFDIV64()
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DAMDGPUISelLowering.cpp1286 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value, in MergeVectorStore()
1331 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, in ScalarizeVectorStore()
1968 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One); in LowerFTRUNC()
2083 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One); in LowerFROUND64()
2169 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, in LowerINT_TO_FP64()
2171 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, in LowerINT_TO_FP64()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp194 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in ScalarizeVecRes_EXTRACT_SUBVECTOR()
262 ISD::EXTRACT_VECTOR_ELT, DL, VT, Op, in ScalarizeVecRes_UnaryOp()
396 ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS, in ScalarizeVecRes_VSETCC()
399 ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS, in ScalarizeVecRes_VSETCC()
449 case ISD::EXTRACT_VECTOR_ELT: in ScalarizeVectorOperand()
1350 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Inputs[Input], in SplitVecRes_VECTOR_SHUFFLE()
1405 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break; in SplitVectorOperand()
1590 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vec, in SplitVecOp_EXTRACT_VECTOR_ELT()
1861 ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Op, in SplitVecOp_CONCAT_VECTORS()
2197 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp1, in WidenVecRes_BinaryCanTrap()
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DLegalizeTypesGeneric.cpp130 ISD::EXTRACT_VECTOR_ELT, dl, ElemVT, CastInOp, in ExpandRes_BITCAST()
245 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
249 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
DLegalizeVectorOps.cpp679 ISD::EXTRACT_VECTOR_ELT, dl, RegSclVT, Value, in ExpandStore()
1035 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS, in UnrollVSETCC()
1038 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS, in UnrollVSETCC()
DLegalizeFloatTypes.cpp74 case ISD::EXTRACT_VECTOR_ELT: in SoftenFloatResult()
159 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in SoftenFloatRes_EXTRACT_VECTOR_ELT()
994 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; in ExpandFloatResult()
1846 case ISD::EXTRACT_VECTOR_ELT: in PromoteFloatResult()
1983 SDValue NewVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IVT, in PromoteFloatRes_EXTRACT_VECTOR_ELT()
DLegalizeIntegerTypes.cpp67 case ISD::EXTRACT_VECTOR_ELT: in PromoteIntegerResult()
407 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0), in PromoteIntRes_EXTRACT_VECTOR_ELT()
884 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break; in PromoteIntegerOperand()
1303 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; in ExpandIntegerResult()
3148 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in PromoteIntRes_EXTRACT_SUBVECTOR()
3241 ISD::EXTRACT_VECTOR_ELT, dl, InElemTy, Op, in PromoteIntRes_CONCAT_VECTORS()
3271 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in PromoteIntOp_EXTRACT_VECTOR_ELT()
3308 ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Incoming, in PromoteIntOp_CONCAT_VECTORS()
DLegalizeDAG.cpp1246 case ISD::EXTRACT_VECTOR_ELT: in LegalizeOp()
3185 case ISD::EXTRACT_VECTOR_ELT: in ExpandNode()
3275 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in ExpandNode()
3279 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1, in ExpandNode()
3924 ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(0), in ExpandNode()
3927 ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(1), in ExpandNode()
4219 Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT || in PromoteNode()
4488 case ISD::EXTRACT_VECTOR_ELT: { in PromoteNode()
4523 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT, in PromoteNode()
4573 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT, in PromoteNode()
DSelectionDAGDumper.cpp218 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; in getOperationName()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h277 EXTRACT_VECTOR_ELT, enumerator
/external/llvm/lib/Target/PowerPC/
DPPCTargetTransformInfo.cpp326 if (ISD == ISD::EXTRACT_VECTOR_ELT || in getVectorInstrCost()
DREADME_ALTIVEC.txt319 Currently EXTRACT_VECTOR_ELT and INSERT_VECTOR_ELT are type-legal only
DPPCISelLowering.cpp470 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); in PPCTargetLowering()
555 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal); in PPCTargetLowering()
558 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal); in PPCTargetLowering()
565 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal); in PPCTargetLowering()
566 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal); in PPCTargetLowering()
567 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal); in PPCTargetLowering()
568 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); in PPCTargetLowering()
570 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal); in PPCTargetLowering()
678 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal); in PPCTargetLowering()
728 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal); in PPCTargetLowering()
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/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp301 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal); in SystemZTargetLowering()
386 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); in SystemZTargetLowering()
387 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); in SystemZTargetLowering()
438 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in SystemZTargetLowering()
850 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VA.getLocVT(), Value, in convertValVTToLocVT()
3917 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in tryBuildVectorShuffle()
4233 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT, in lowerEXTRACT_VECTOR_ELT()
4403 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
4634 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op, in combineExtract()
4648 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineTruncateExtract()
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DSystemZISelDAGToDAG.cpp678 if (Index.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in selectBDVAddr12Only()
1082 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in tryScatter()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp699 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand); in X86TargetLowering()
807 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); in X86TargetLowering()
881 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
907 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); in X86TargetLowering()
911 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); in X86TargetLowering()
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); in X86TargetLowering()
1015 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); in X86TargetLowering()
1016 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); in X86TargetLowering()
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); in X86TargetLowering()
1023 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); in X86TargetLowering()
[all …]
/external/llvm/test/CodeGen/ARM/
Dvpadd.ll155 ; Legalization produces a EXTRACT_VECTOR_ELT DAG node which performs an extend from
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp102 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
1653 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, in LowerCall()
1655 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, in LowerCall()
2307 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, in LowerReturn()
2326 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, in LowerReturn()
4026 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res, in LowerFCOPYSIGN()
4155 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in CombineVMOVDRRCandidateWithVecOp()
4916 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant, in LowerConstantFP()
4947 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant, in LowerConstantFP()
4964 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant, in LowerConstantFP()
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/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp507 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in AArch64TargetLowering()
662 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); in addTypeForNEON()
2297 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
4867 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) { in ReconstructShuffle()
5609 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV), in LowerVECTOR_SHUFFLE()
6251 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in LowerBUILD_VECTOR()
6390 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!"); in LowerEXTRACT_VECTOR_ELT()
6420 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec, in LowerEXTRACT_VECTOR_ELT()
7988 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in tryCombineFixedPointConvert()
8012 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane); in tryCombineFixedPointConvert()
[all …]
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp1677 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp, in LowerCONCAT_VECTORS()
1972 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val, in LowerSTOREVector()
2228 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P, in LowerFormalArguments()
2230 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P, in LowerFormalArguments()
2274 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P, in LowerFormalArguments()
2498 TmpVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in LowerReturn()
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp256 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom); in addMSAIntType()
305 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal); in addMSAFloatType()
376 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
1758 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), in lowerINTRINSIC_WO_CHAIN()
1776 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), in lowerINTRINSIC_WO_CHAIN()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp241 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
244 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
868 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, in LowerCall_32()
871 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, in LowerCall_32()
1470 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal); in SparcTargetLowering()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1767 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT, in HexagonTargetLowering()
1792 setOperationAction(ISD::EXTRACT_VECTOR_ELT, NativeVT, Custom); in HexagonTargetLowering()
2416 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT ? in LowerEXTRACT_VECTOR()
2587 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR(Op, DAG); in LowerOperation()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td413 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
538 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",

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