| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 356 SmallVectorImpl<CCValAssign> &RVLocs, in AnalyzeReturnValues() argument
362 std::reverse(RVLocs.begin(), RVLocs.end()); in AnalyzeReturnValues()
528 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
535 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
539 AnalyzeReturnValues(CCInfo, RVLocs, Outs); in LowerReturn()
545 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
546 CCValAssign &VA = RVLocs[i]; in LowerReturn()
719 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
720 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
723 AnalyzeReturnValues(CCInfo, RVLocs, Ins); in LowerCallResult()
[all …]
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 394 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
398 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerReturn()
413 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
414 CCValAssign &VA = RVLocs[i]; in LowerReturn()
442 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
443 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerCallResult()
454 for (auto &Val : RVLocs) { in LowerCallResult()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2034 SmallVector<CCValAssign, 16> RVLocs; in FinishCall() local
2035 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context); in FinishCall()
2039 if (RVLocs.size() == 2 && RetVT == MVT::f64) { in FinishCall()
2042 MVT DestVT = RVLocs[0].getValVT(); in FinishCall()
2047 .addReg(RVLocs[0].getLocReg()) in FinishCall()
2048 .addReg(RVLocs[1].getLocReg())); in FinishCall()
2050 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2051 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
2056 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!"); in FinishCall()
2057 MVT CopyVT = RVLocs[0].getValVT(); in FinishCall()
[all …]
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| D | ARMISelLowering.cpp | 1431 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
1432 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
1439 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
1440 CCValAssign VA = RVLocs[i]; in LowerCallResult()
1458 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1472 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1476 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
2221 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
2222 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
2268 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
[all …]
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1076 const SmallVectorImpl<CCValAssign> &RVLocs, in LowerCallResult() argument
1081 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerCallResult()
1082 const CCValAssign &VA = RVLocs[i]; in LowerCallResult()
1142 SmallVector<CCValAssign, 16> RVLocs; in LowerCCCCallTo() local
1144 CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCCCCallTo()
1247 return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals); in LowerCCCCallTo()
1456 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
1457 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
1478 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
1481 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
[all …]
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 213 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn_32() local
216 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn_32()
229 i != RVLocs.size(); in LowerReturn_32()
231 CCValAssign &VA = RVLocs[i]; in LowerReturn_32()
251 VA = RVLocs[++i]; // skip ahead to next loc in LowerReturn_32()
296 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn_64() local
299 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn_64()
313 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn_64()
314 CCValAssign &VA = RVLocs[i]; in LowerReturn_64()
342 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 1393 SmallVector<CCValAssign, 16> RVLocs; in finishCall() local
1394 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); in finishCall()
1396 CCValAssign &VA = RVLocs[0]; in finishCall()
1397 assert(RVLocs.size() == 1 && "No support for multi-reg return values!"); in finishCall()
1482 SmallVector<CCValAssign, 16> RVLocs; in fastLowerCall() local
1483 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context); in fastLowerCall()
1485 if (RVLocs.size() > 1) in fastLowerCall()
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| D | PPCISelLowering.cpp | 4318 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
4319 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
4324 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerCallResult()
4325 CCValAssign &VA = RVLocs[i]; in LowerCallResult()
5771 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
5772 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
5783 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
5784 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
5792 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
5793 CCValAssign &VA = RVLocs[i]; in LowerReturn()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1212 SmallVector<CCValAssign, 16> RVLocs; in finishCall() local
1213 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); in finishCall()
1217 if (RVLocs.size() != 1) in finishCall()
1220 MVT CopyVT = RVLocs[0].getValVT(); in finishCall()
1230 ResultReg).addReg(RVLocs[0].getLocReg()); in finishCall()
1231 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
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| D | MipsISelLowering.cpp | 2824 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
2825 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
2830 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
2831 CCValAssign &VA = RVLocs[i]; in LowerCallResult()
2834 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), in LowerCallResult()
2835 RVLocs[i].getLocVT(), InFlag); in LowerCallResult()
3104 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
3105 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
3138 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
3142 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerReturn()
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 564 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
567 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
577 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
578 CCValAssign &VA = RVLocs[i]; in LowerReturn()
622 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
624 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
630 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
632 RVLocs[i].getLocReg(), in LowerCallResult()
633 RVLocs[i].getValVT(), InFlag).getValue(1); in LowerCallResult()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 3164 SmallVector<CCValAssign, 16> RVLocs; in fastLowerCall() local
3165 CCState CCRetInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, in fastLowerCall()
3171 for (unsigned i = 0; i != RVLocs.size(); ++i) { in fastLowerCall()
3172 CCValAssign &VA = RVLocs[i]; in fastLowerCall()
3213 CLI.NumResultRegs = RVLocs.size(); in fastLowerCall()
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| D | X86ISelLowering.cpp | 2179 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
2180 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
2201 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
2202 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext()); in LowerReturn()
2213 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
2214 CCValAssign &VA = RVLocs[i]; in LowerReturn()
2384 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
2386 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
2391 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerCallResult()
2392 CCValAssign &VA = RVLocs[i]; in LowerCallResult()
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 3004 SmallVector<CCValAssign, 16> RVLocs; in finishCall() local
3005 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); in finishCall()
3009 if (RVLocs.size() != 1) in finishCall()
3013 MVT CopyVT = RVLocs[0].getValVT(); in finishCall()
3022 .addReg(RVLocs[0].getLocReg()); in finishCall()
3023 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
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| D | AArch64ISelLowering.cpp | 2650 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
2651 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
2656 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
2657 CCValAssign VA = RVLocs[i]; in LowerCallResult()
3225 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
3226 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
3239 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
3240 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
3247 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size(); in LowerReturn()
3249 CCValAssign &VA = RVLocs[i]; in LowerReturn()
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