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Searched refs:Rn (Results 1 – 25 of 54) sorted by relevance

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/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td617 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
618 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
619 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
620 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
621 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
622 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
623 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
624 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
625 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
626 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
[all …]
DAArch64InstrFormats.td1066 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
1067 bits<5> Rn;
1068 let Inst{9-5} = Rn;
1230 def : Pat<(node GPR64:$Rn, tbz_imm0_31_diag:$imm, bb:$target),
1231 (!cast<Instruction>(NAME#"W") (EXTRACT_SUBREG GPR64:$Rn, sub_32),
1275 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
1276 [(set regtype:$Rd, (node regtype:$Rn))]>,
1279 bits<5> Rn;
1283 let Inst{9-5} = Rn;
1314 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
[all …]
DAArch64InstrAtomics.td45 def : Pat<(relaxed_load<atomic_load_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
47 (LDRBBroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$offset)>;
48 def : Pat<(relaxed_load<atomic_load_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
50 (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>;
51 def : Pat<(relaxed_load<atomic_load_8> (am_indexed8 GPR64sp:$Rn,
53 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
55 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
56 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
60 def : Pat<(relaxed_load<atomic_load_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
62 (LDRHHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>;
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td281 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
287 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
312 bits<4> Rn;
324 bits<4> Rn;
327 let Inst{19-16} = Rn;
363 bits<4> Rn;
366 let Inst{19-16} = Rn;
396 bits<4> Rn;
399 let Inst{19-16} = Rn;
408 bits<4> Rn;
[all …]
DARMInstrInfo.td1224 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1231 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1232 iii, opc, "\t$Rd, $Rn, $imm",
1233 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1236 bits<4> Rn;
1239 let Inst{19-16} = Rn;
1244 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1245 iir, opc, "\t$Rd, $Rn, $Rm",
1246 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1249 bits<4> Rn;
[all …]
DARMInstrThumb.td373 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
384 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
405 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
406 "add", "\t$Rdn, $sp, $Rn", []>,
417 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
732 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
733 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
734 bits<3> Rn;
736 let Inst{10-8} = Rn;
746 "$Rn = $wb", IIC_iLoad_mu>,
[all …]
DARMInstrNEON.td611 : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn),
613 [(set DPair:$dst, (v2f64 (load GPR:$Rn)))]>;
618 : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
620 [(store (v2f64 DPair:$src), GPR:$Rn)]>;
668 (ins AddrMode:$Rn), IIC_VLD1,
669 "vld1", Dt, "$Vd, $Rn", "", []> {
671 let Inst{4} = Rn{4};
676 (ins AddrMode:$Rn), IIC_VLD1x2,
677 "vld1", Dt, "$Vd, $Rn", "", []> {
679 let Inst{5-4} = Rn{5-4};
[all …]
DARMSchedule.td18 // Rd <- ADD Rn, Rm, <shift> Rs
20 // 2 | Rn: 1 Rm: 4 Rs: 4 | uop T0, Rm, Rs - P01 - 3
21 // | | uopc Rd, Rn, T0 - P01 - 1
24 // and one cycle after the result in Rn is available. The micro-ops can execute
27 // that the resource P01 is needed and that the latency to Rn is different than
28 // the latency to Rm and Rs. The scheduler can decrease Rn's producer latency by
DARMInstrFormats.td75 // The instruction has an Rn register operand.
77 // it doesn't have a Rn operand.
666 bits<4> Rn;
669 let Inst{19-16} = Rn;
684 bits<4> Rn;
687 let Inst{19-16} = Rn;
700 // {17-14} Rn
724 let Inst{19-16} = addr{12-9}; // Rn
754 // {12-9} Rn
764 let Inst{19-16} = addr; // Rn
[all …]
DARMInstrVFP.td123 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
125 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
131 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
134 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
140 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
143 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
151 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
153 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
163 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
166 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
[all …]
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1319 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeCopMemInstruction() local
1369 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeCopMemInstruction()
1465 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeAddrMode2IdxInstruction() local
1484 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1504 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1525 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
1570 unsigned Rn = fieldFromInstruction(Val, 13, 4); in DecodeSORegMemOperand() local
1595 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeSORegMemOperand()
1615 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeAddrMode3Instruction() local
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/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-thumbv7.txt46 # Writeback is not allowed is Rn is in the target register list.
63 # if Rn = '1111' then SEE LDRD (literal)
160 # invalid STRi12 Rn=PC
165 # invalid STRi8 Rn=PC
170 # invalid STRs Rn=PC
175 # invalid STRBi12 Rn=PC
180 # invalid STRBi8 Rn=PC
185 # invalid STRBs Rn=PC
190 # invalid STRHi12 Rn=PC
195 # invalid STRHi8 Rn=PC
[all …]
/external/vixl/src/vixl/a64/
Dsimulator-a64.cc843 const Instruction* target = Instruction::Cast(xreg(instr->Rn())); in VisitUnconditionalBranchToRegister()
899 reg(reg_size, instr->Rn(), instr->RnMode()), in AddSubHelper()
907 reg(reg_size, instr->Rn(), instr->RnMode()), in AddSubHelper()
956 reg(reg_size, instr->Rn()), in VisitAddSubWithCarry()
984 int64_t op1 = reg(reg_size, instr->Rn()); in LogicalHelper()
1025 int64_t op1 = reg(reg_size, instr->Rn()); in ConditionalCompareHelper()
1081 uintptr_t address = AddressModeHelper(instr->Rn(), offset, addrmode); in LoadStoreHelper()
1179 uintptr_t address = AddressModeHelper(instr->Rn(), offset, addrmode); in LoadStorePairHelper()
1297 unsigned rn = instr->Rn(); in VisitLoadStoreExclusive()
1567 uint64_t new_val = xreg(instr->Rn()); in VisitConditionalSelect()
[all …]
Dassembler-a64.cc648 Emit(BR | Rn(xn)); in br()
654 Emit(BLR | Rn(xn)); in blr()
660 Emit(RET | Rn(xn)); in ret()
735 Emit(op | (vd.IsQ() ? NEON_Q : 0) | Rm(vm) | Rn(vn) | Rd(vd)); in NEONTable()
1055 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd)); in lslv()
1064 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd)); in lsrv()
1073 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd)); in asrv()
1082 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd)); in rorv()
1094 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd)); in bfm()
1105 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd)); in sbfm()
[all …]
Ddisasm-a64.h133 return (instr->Rn() == kZeroRegCode); in RnIsZROrSP()
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp653 unsigned Rn = fieldFromInstruction(Insn, 5, 5); in DecodeFMOVLaneInstruction() local
658 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); in DecodeFMOVLaneInstruction()
661 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); in DecodeFMOVLaneInstruction()
744 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeThreeAddrSRegInstruction() local
772 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
793 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
839 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeUnsignedLdStInstruction() local
890 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); in DecodeUnsignedLdStInstruction()
900 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeSignedLdStInstruction() local
958 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); in DecodeSignedLdStInstruction()
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/external/v8/src/arm64/
Dassembler-arm64.cc906 instr->following()->Rn() == kZeroRegCode)); in IsConstantPoolAt()
942 Emit(BLR | Rn(xzr)); in EmitPoolGuard()
963 Emit(BR | Rn(xn)); in br()
973 Emit(BLR | Rn(xn)); in blr()
980 Emit(RET | Rn(xn)); in ret()
1252 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd)); in lslv()
1261 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd)); in lsrv()
1270 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd)); in asrv()
1279 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd)); in rorv()
1291 Rn(rn) | Rd(rd)); in bfm()
[all …]
Dsimulator-arm64.cc905 reg<T>(instr->Rn()), in AddSubWithCarry()
981 T op1 = reg<T>(instr->Rn()); in Extract()
1338 Instruction* target = reg<Instruction*>(instr->Rn()); in VisitUnconditionalBranchToRegister()
1342 if (instr->Rn() == 31) { in VisitUnconditionalBranchToRegister()
1397 reg<T>(instr->Rn(), instr->RnMode()), in AddSubHelper()
1404 reg<T>(instr->Rn(), instr->RnMode()), in AddSubHelper()
1490 T op1 = reg<T>(instr->Rn()); in LogicalHelper()
1537 T op1 = reg<T>(instr->Rn()); in ConditionalCompareHelper()
1591 unsigned addr_reg = instr->Rn(); in LoadStoreHelper()
1690 unsigned addr_reg = instr->Rn(); in LoadStorePairHelper()
[all …]
Ddisasm-arm64.h53 return (instr->Rn() == kZeroRegCode); in RnIsZROrSP()
Ddisasm-arm64.cc369 bool rn_is_rm = (instr->Rn() == instr->Rm()); in VisitConditionalSelect()
505 if (instr->Rn() == instr->Rm()) { in VisitExtract()
546 if (instr->Rn() == kLinkRegCode) { in VisitUnconditionalBranchToRegister()
1286 case 'n': reg_num = instr->Rn(); break; in SubstituteRegisterField()
1615 if (((instr->Rd() == kZeroRegCode) || (instr->Rn() == kZeroRegCode)) && in SubstituteExtendField()
/external/v8/src/arm/
Ddisasm-arm.cc90 void FormatNeonMemory(int Rn, int align, int Rm);
415 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) { in FormatNeonMemory() argument
417 "[r%d", Rn); in FormatNeonMemory()
1726 int Rn = instr->VnValue(); in DecodeSpecialCondition() local
1735 FormatNeonMemory(Rn, align, Rm); in DecodeSpecialCondition()
1739 int Rn = instr->VnValue(); in DecodeSpecialCondition() local
1748 FormatNeonMemory(Rn, align, Rm); in DecodeSpecialCondition()
1756 int Rn = instr->Bits(19, 16); in DecodeSpecialCondition() local
1760 "pld [r%d]", Rn); in DecodeSpecialCondition()
1763 "pld [r%d, #-%d]", Rn, offset); in DecodeSpecialCondition()
[all …]
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp873 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getThumbAddrModeRegRegOpValue() local
875 return (Rm << 3) | Rn; in getThumbAddrModeRegRegOpValue()
1080 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getLdStSORegOpValue() local
1099 Binary |= Rn << 13; in getLdStSORegOpValue()
1116 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getAddrMode2OpValue() local
1118 Binary |= Rn << 14; in getAddrMode2OpValue()
1192 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. in getAddrMode3OpValue() local
1200 return (Rn << 9) | (1 << 13); in getAddrMode3OpValue()
1202 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getAddrMode3OpValue() local
1210 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13); in getAddrMode3OpValue()
[all …]
/external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/es-ES/
Des-ES_kdt_g2p.pkb11 �U�����9���rEL_^���ZdM��e���8�X��4�չE%Mg�>�h�i�>K'`(�>~B`�Z�,�Rn
/external/llvm/test/CodeGen/AArch64/
Dzero-reg.ll23 ; instruction (0b11111 in the Rn field would mean "sp").
/external/vixl/examples/
Dnon-const-visitor.h41 int rn = instr->Rn(); in VisitAddSubShifted()

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