/external/llvm/lib/Target/X86/ |
D | X86TargetTransformInfo.cpp | 562 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost() 565 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, in getCastInstrCost() 567 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, in getCastInstrCost() 569 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, in getCastInstrCost() 570 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, in getCastInstrCost() 612 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, in getCastInstrCost() 614 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, in getCastInstrCost() 616 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost() 618 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, in getCastInstrCost() 620 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, in getCastInstrCost() [all …]
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D | X86ISelLowering.cpp | 749 setOperationAction(ISD::ZERO_EXTEND, VT, Expand); in X86TargetLowering() 1139 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom); in X86TargetLowering() 1140 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom); in X86TargetLowering() 1141 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom); in X86TargetLowering() 1444 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom); in X86TargetLowering() 1445 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom); in X86TargetLowering() 1649 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom); in X86TargetLowering() 1651 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom); in X86TargetLowering() 1655 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom); in X86TargetLowering() 1816 setTargetDAGCombine(ISD::ZERO_EXTEND); in X86TargetLowering() [all …]
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D | X86FastISel.cpp | 1082 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : in X86SelectRet() 1372 ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND, in X86SelectZExt() 2974 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall() 2986 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64TargetTransformInfo.cpp | 198 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost() 200 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost() 202 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost() 204 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, in getCastInstrCost() 206 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost() 208 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost() 210 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, in getCastInstrCost() 212 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
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D | AArch64ISelLowering.cpp | 491 setTargetDAGCombine(ISD::ZERO_EXTEND); in AArch64TargetLowering() 1578 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in getAArch64XALUOOp() 1930 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerVectorINT_TO_FP() 2079 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND) in skipExtensionForVectorMULL() 2112 if (N->getOpcode() == ISD::ZERO_EXTEND) in isZeroExtended() 3008 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall() 3014 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg); in LowerCall() 3262 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerReturn() 3804 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val); in LowerCTPOP() 3813 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV); in LowerCTPOP() [all …]
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/external/llvm/lib/Target/ARM/ |
D | ARMTargetTransformInfo.cpp | 80 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost() 82 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost() 88 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost() 90 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost() 92 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost() 94 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost() 96 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
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D | ARMSelectionDAGInfo.cpp | 97 Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); in EmitSpecializedLibcall()
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D | ARMISelLowering.cpp | 619 setTargetDAGCombine(ISD::ZERO_EXTEND); in ARMTargetLowering() 1640 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall() 3951 CastOpc = ISD::ZERO_EXTEND; in LowerVectorINT_TO_FP() 4467 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts); in lowerCTPOP16BitElements() 4473 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted); in lowerCTPOP16BitElements() 4509 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2); in lowerCTPOP32BitElements() 4515 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted); in lowerCTPOP32BitElements() 6217 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N)) in isZeroExtended() 6292 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND) in SkipExtensionForVMULL() 6546 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0); in LowerUDIV() [all …]
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/external/llvm/lib/Target/NVPTX/ |
D | NVPTXISelLowering.cpp | 1170 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt); in LowerCall() 1185 Elt0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt0); in LowerCall() 1186 Elt1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt1); in LowerCall() 1230 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal); in LowerCall() 1237 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal); in LowerCall() 1249 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal); in LowerCall() 1259 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal); in LowerCall() 1300 unsigned opc = ISD::ZERO_EXTEND; in LowerCall() 2008 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3); in LowerSTOREi1() 2387 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal); in LowerReturn() [all …]
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/external/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 392 ZERO_EXTEND, enumerator
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/external/mesa3d/src/gallium/drivers/radeon/ |
D | AMDILISelLowering.cpp | 184 setOperationAction(ISD::ZERO_EXTEND, MVT::v2i64, Expand); in InitAMDILLowering() 199 setOperationAction(ISD::ZERO_EXTEND, MVT::v2f64, Expand); in InitAMDILLowering() 434 Data = DAG.getNode(ISD::ZERO_EXTEND, DL, IVT, Data); in LowerSIGN_EXTEND_INREG()
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | DAGCombiner.cpp | 990 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteOperand() 1402 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); in visit() 1490 case ISD::ZERO_EXTEND: in combine() 1773 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); in visitADD() 2538 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); in visitMULHU() 2539 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); in visitMULHU() 2647 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); in visitUMUL_LOHI() 2648 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); in visitUMUL_LOHI() 2728 if ((N0.getOpcode() == ISD::ZERO_EXTEND || in SimplifyBinOpWithSameOpcodeHands() 3073 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), in visitAND() [all …]
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D | TargetLowering.cpp | 372 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND, in ShrinkDemandedOp() 918 case ISD::ZERO_EXTEND: { in SimplifyDemandedBits() 967 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, in SimplifyDemandedBits() 1084 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); in SimplifyDemandedBits() 1345 if (N0->getOpcode() == ISD::ZERO_EXTEND) { in SimplifySetCC() 1452 if (N0.getOpcode() == ISD::ZERO_EXTEND) { in SimplifySetCC() 2082 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); in SimplifySetCC()
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D | LegalizeIntegerTypes.cpp | 106 case ISD::ZERO_EXTEND: in PromoteIntegerResult() 348 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteIntRes_Constant() 458 if (N->getOpcode() == ISD::ZERO_EXTEND) in PromoteIntRes_INT_EXTEND() 834 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]); in PromoteIntRes_VAARG() 836 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]); in PromoteIntRes_VAARG() 910 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; in PromoteIntegerOperand() 1329 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; in ExpandIntegerResult() 2596 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0)); in ExpandIntRes_ZERO_EXTEND()
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D | LegalizeVectorOps.cpp | 294 case ISD::ZERO_EXTEND: in LegalizeOp() 452 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : in PromoteINT_TO_FP()
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D | LegalizeVectorTypes.cpp | 100 case ISD::ZERO_EXTEND: in ScalarizeVectorResult() 437 case ISD::ZERO_EXTEND: in ScalarizeVectorOperand() 660 case ISD::ZERO_EXTEND: in SplitVectorResult() 1446 case ISD::ZERO_EXTEND: in SplitVectorOperand() 2081 case ISD::ZERO_EXTEND: in WidenVectorResult() 2974 case ISD::ZERO_EXTEND: in WidenVectorOperand() 3062 case ISD::ZERO_EXTEND: in WidenVecOp_EXTEND()
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D | LegalizeDAG.cpp | 2763 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, in PromoteLegalINT_TO_FP() 3526 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) && in ExpandNode() 3531 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo); in ExpandNode() 3603 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, in ExpandNode() 3684 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); in ExpandNode() 4235 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode() 4257 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode() 4374 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteNode() 4387 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteNode()
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D | SelectionDAG.cpp | 237 return ISD::ZERO_EXTEND; in getExtForLoadExtType() 1025 getNode(ISD::ZERO_EXTEND, DL, VT, Op) : in getZExtOrTrunc() 2292 case ISD::ZERO_EXTEND: { in computeKnownBits() 2878 case ISD::ZERO_EXTEND: in getNode() 3042 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) in getNode() 3048 case ISD::ZERO_EXTEND: in getNode() 3058 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) in getNode() 3059 return getNode(ISD::ZERO_EXTEND, DL, VT, in getNode() 3076 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || in getNode() 3102 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || in getNode() [all …]
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D | SelectionDAGDumper.cpp | 241 case ISD::ZERO_EXTEND: return "zero_extend"; in getOperationName()
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZISelDAGToDAG.cpp | 676 if (Index.getOpcode() == ISD::ZERO_EXTEND) in selectBDVAddr12Only() 810 case ISD::ZERO_EXTEND: in expandRxSBG() 1212 case ISD::ZERO_EXTEND: in Select()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCISelLowering.cpp | 856 setTargetDAGCombine(ISD::ZERO_EXTEND); in PPCTargetLowering() 2271 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); in LowerSETCC() 4664 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg); in LowerCall_32SVR4() 4955 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4() 5526 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_Darwin() 5593 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg); in LowerCall_Darwin() 5805 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerReturn() 5995 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(DAG.getDataLayout()), in LowerSTORE() 6459 SINT.getOpcode() == ISD::ZERO_EXTEND)) && in LowerINT_TO_FP() 6485 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ? in LowerINT_TO_FP() [all …]
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/external/llvm/lib/Target/Sparc/ |
D | SparcISelLowering.cpp | 325 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64() 343 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); in LowerReturn_64() 817 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32() 1170 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64() 1224 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, in LowerCall_64() 2850 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo); in LowerADDC_ADDE_SUBC_SUBE() 2851 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi); in LowerADDC_ADDE_SUBC_SUBE()
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/external/llvm/test/CodeGen/AArch64/ |
D | rm_redundant_cmp.ll | 246 ; The optimization of ZERO_EXTEND and SIGN_EXTEND in type legalization stage can't assert
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonISelLowering.cpp | 739 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall() 1212 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, PopOut); in LowerCTPOP() 1230 : ISD::ZERO_EXTEND; in LowerSETCC() 1272 SDValue X1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op1); in LowerVSELECT() 1273 SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2); in LowerVSELECT()
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/external/llvm/lib/Target/BPF/ |
D | BPFISelLowering.cpp | 324 Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
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