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/external/llvm/test/CodeGen/X86/
D2008-07-19-movups-spills.ll7 external global <4 x float>, align 1 ; <<4 x float>*>:0 [#uses=2]
8 external global <4 x float>, align 1 ; <<4 x float>*>:1 [#uses=1]
9 external global <4 x float>, align 1 ; <<4 x float>*>:2 [#uses=1]
10 external global <4 x float>, align 1 ; <<4 x float>*>:3 [#uses=1]
11 external global <4 x float>, align 1 ; <<4 x float>*>:4 [#uses=1]
12 external global <4 x float>, align 1 ; <<4 x float>*>:5 [#uses=1]
13 external global <4 x float>, align 1 ; <<4 x float>*>:6 [#uses=1]
14 external global <4 x float>, align 1 ; <<4 x float>*>:7 [#uses=1]
15 external global <4 x float>, align 1 ; <<4 x float>*>:8 [#uses=1]
16 external global <4 x float>, align 1 ; <<4 x float>*>:9 [#uses=1]
[all …]
Dlarge-gep-chain.ll4 %0 = type { i32, float* }
24 %tmp = getelementptr inbounds float, float* null, i64 1
25 %tmp3 = getelementptr inbounds float, float* %tmp, i64 1
26 %tmp4 = getelementptr inbounds float, float* %tmp3, i64 1
27 %tmp5 = getelementptr inbounds float, float* %tmp4, i64 1
28 %tmp6 = getelementptr inbounds float, float* %tmp5, i64 1
29 %tmp7 = getelementptr inbounds float, float* %tmp6, i64 1
30 %tmp8 = getelementptr inbounds float, float* %tmp7, i64 1
31 %tmp9 = getelementptr inbounds float, float* %tmp8, i64 1
32 %tmp10 = getelementptr inbounds float, float* %tmp9, i64 1
[all …]
Dfmul-combines.ll5 define float @fmul2_f32(float %x) {
6 %y = fmul float %x, 2.0
7 ret float %y
15 define <4 x float> @fmul2_v4f32(<4 x float> %x) {
16 %y = fmul <4 x float> %x, <float 2.0, float 2.0, float 2.0, float 2.0>
17 ret <4 x float> %y
23 define <4 x float> @constant_fold_fmul_v4f32(<4 x float> %x) {
24 …%y = fmul <4 x float> <float 4.0, float 4.0, float 4.0, float 4.0>, <float 2.0, float 2.0, float 2…
25 ret <4 x float> %y
31 define <4 x float> @fmul0_v4f32(<4 x float> %x) #0 {
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dbig_alu.ll6 …float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 …
8 %0 = extractelement <4 x float> %reg0, i32 0
9 %1 = extractelement <4 x float> %reg0, i32 1
10 %2 = extractelement <4 x float> %reg0, i32 2
11 %3 = extractelement <4 x float> %reg0, i32 3
12 %4 = extractelement <4 x float> %reg1, i32 0
13 %5 = extractelement <4 x float> %reg9, i32 0
14 %6 = extractelement <4 x float> %reg8, i32 0
15 %7 = fcmp ugt float %6, 0.000000e+00
16 %8 = select i1 %7, float %4, float %5
[all …]
Dpv.ll6 …float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 …
8 %0 = extractelement <4 x float> %reg1, i32 0
9 %1 = extractelement <4 x float> %reg1, i32 1
10 %2 = extractelement <4 x float> %reg1, i32 2
11 %3 = extractelement <4 x float> %reg1, i32 3
12 %4 = extractelement <4 x float> %reg2, i32 0
13 %5 = extractelement <4 x float> %reg2, i32 1
14 %6 = extractelement <4 x float> %reg2, i32 2
15 %7 = extractelement <4 x float> %reg2, i32 3
16 %8 = extractelement <4 x float> %reg3, i32 0
[all …]
Dr600-export-fix.ll13 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
15 %0 = extractelement <4 x float> %reg1, i32 0
16 %1 = extractelement <4 x float> %reg1, i32 1
17 %2 = extractelement <4 x float> %reg1, i32 2
18 %3 = extractelement <4 x float> %reg1, i32 3
19 …%4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x…
20 %5 = extractelement <4 x float> %4, i32 0
21 %6 = fmul float %5, %0
22 …%7 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x…
23 %8 = extractelement <4 x float> %7, i32 1
[all …]
Dkcache-fold.ll7 %0 = load <4 x float>, <4 x float> addrspace(8)* null
8 %1 = extractelement <4 x float> %0, i32 0
9 …%2 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x…
10 %3 = extractelement <4 x float> %2, i32 0
11 …%4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x…
12 %5 = extractelement <4 x float> %4, i32 0
13 %6 = fcmp ogt float %1, 0.000000e+00
14 %7 = select i1 %6, float %3, float %5
15 %8 = load <4 x float>, <4 x float> addrspace(8)* null
16 %9 = extractelement <4 x float> %8, i32 1
[all …]
Dload-input-fold.ll3 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x f…
5 %0 = extractelement <4 x float> %reg1, i32 0
6 %1 = extractelement <4 x float> %reg1, i32 1
7 %2 = extractelement <4 x float> %reg1, i32 2
8 %3 = extractelement <4 x float> %reg1, i32 3
9 %4 = extractelement <4 x float> %reg2, i32 0
10 %5 = extractelement <4 x float> %reg2, i32 1
11 %6 = extractelement <4 x float> %reg2, i32 2
12 %7 = extractelement <4 x float> %reg2, i32 3
13 %8 = extractelement <4 x float> %reg3, i32 0
[all …]
Dvgpr-spill-emergency-stack-slot-compute.ll37 …void @spill_vgpr_compute(<4 x float> %arg6, float addrspace(1)* %arg, i32 %arg1, i32 %arg2, float …
40 %tmp7 = extractelement <4 x float> %arg6, i32 0
41 %tmp8 = extractelement <4 x float> %arg6, i32 1
42 %tmp9 = extractelement <4 x float> %arg6, i32 2
43 %tmp10 = extractelement <4 x float> %arg6, i32 3
44 %tmp11 = bitcast float %arg5 to i32
48 %tmp13 = phi float [ 0.000000e+00, %bb ], [ %tmp338, %bb145 ]
49 %tmp14 = phi float [ 0.000000e+00, %bb ], [ %tmp337, %bb145 ]
50 %tmp15 = phi float [ 0.000000e+00, %bb ], [ %tmp336, %bb145 ]
51 %tmp16 = phi float [ 0.000000e+00, %bb ], [ %tmp339, %bb145 ]
[all …]
Dsi-spill-cf.ll11 %0 = call float @llvm.SI.load.const(<16 x i8> undef, i32 16)
12 %1 = call float @llvm.SI.load.const(<16 x i8> undef, i32 32)
13 %2 = call float @llvm.SI.load.const(<16 x i8> undef, i32 80)
14 %3 = call float @llvm.SI.load.const(<16 x i8> undef, i32 84)
15 %4 = call float @llvm.SI.load.const(<16 x i8> undef, i32 88)
16 %5 = call float @llvm.SI.load.const(<16 x i8> undef, i32 96)
17 %6 = call float @llvm.SI.load.const(<16 x i8> undef, i32 100)
18 %7 = call float @llvm.SI.load.const(<16 x i8> undef, i32 104)
19 %8 = call float @llvm.SI.load.const(<16 x i8> undef, i32 112)
20 %9 = call float @llvm.SI.load.const(<16 x i8> undef, i32 116)
[all …]
Dsi-sgpr-spill.ll24 …float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32…
28 %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 96)
29 %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 100)
30 %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 104)
31 %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 112)
32 %27 = call float @llvm.SI.load.const(<16 x i8> %22, i32 116)
33 %28 = call float @llvm.SI.load.const(<16 x i8> %22, i32 120)
34 %29 = call float @llvm.SI.load.const(<16 x i8> %22, i32 128)
35 %30 = call float @llvm.SI.load.const(<16 x i8> %22, i32 132)
36 %31 = call float @llvm.SI.load.const(<16 x i8> %22, i32 140)
[all …]
Dswizzle-export.ll9 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
11 %0 = extractelement <4 x float> %reg1, i32 0
12 %1 = extractelement <4 x float> %reg1, i32 1
13 %2 = extractelement <4 x float> %reg1, i32 2
14 %3 = extractelement <4 x float> %reg1, i32 3
15 %4 = load <4 x float>, <4 x float> addrspace(8)* null
16 %5 = extractelement <4 x float> %4, i32 1
17 %6 = load <4 x float>, <4 x float> addrspace(8)* null
18 %7 = extractelement <4 x float> %6, i32 2
19 %8 = load <4 x float>, <4 x float> addrspace(8)* null
[all …]
Dschedule-vs-if-nested-loop.ll4 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
6 %0 = extractelement <4 x float> %reg1, i32 0
7 %1 = extractelement <4 x float> %reg1, i32 1
8 %2 = extractelement <4 x float> %reg1, i32 2
9 %3 = extractelement <4 x float> %reg1, i32 3
10 %4 = fcmp ult float %0, 0.000000e+00
11 %5 = select i1 %4, float 1.000000e+00, float 0.000000e+00
12 %6 = fsub float -0.000000e+00, %5
13 %7 = fptosi float %6 to i32
14 %8 = bitcast i32 %7 to float
[all …]
/external/llvm/test/CodeGen/ARM/
D2009-11-13-ScavengerAssert2.ll4 %bar = type { %quad, float, float, [3 x %quuz*], [3 x %bar*], [2 x %bar*], [3 x i8], i8 }
6 %foo = type { i8, %quux, %quad, float, [64 x %quuz], [128 x %bar], i32, %baz, %baz }
7 %quad = type { [4 x float] }
8 %quux = type { [4 x %quuz*], [4 x float], i32 }
22 %0 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=0]
23 %1 = fsub float 0.000000e+00, undef ; <float> [#uses=1]
24 %2 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=2]
25 %3 = load float, float* %2, align 4 ; <float> [#uses=1]
26 %4 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1]
27 %5 = fsub float %3, undef ; <float> [#uses=2]
[all …]
D2009-11-13-VRRewriterCrash.ll5 %bar = type { %quad, float, float, [3 x %quuz*], [3 x %bar*], [2 x %bar*], [3 x i8], i8 }
7 %foo = type { i8, %quux, %quad, float, [64 x %quuz], [128 x %bar], i32, %baz, %baz }
8 %quad = type { [4 x float] }
9 %quux = type { [4 x %quuz*], [4 x float], i32 }
24 %1 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=1]
25 %2 = fsub float 0.000000e+00, undef ; <float> [#uses=1]
26 %3 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1]
27 %4 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 2 ; <float*> [#uses=1]
28 %5 = fsub float 0.000000e+00, undef ; <float> [#uses=1]
29 %6 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=1]
[all …]
D2009-11-07-SubRegAsmPrinting.ll9 %0 = load float, float* null, align 4 ; <float> [#uses=2]
10 %1 = fmul float %0, undef ; <float> [#uses=2]
11 %2 = fmul float 0.000000e+00, %1 ; <float> [#uses=2]
12 %3 = fmul float %0, %1 ; <float> [#uses=1]
13 %4 = fadd float 0.000000e+00, %3 ; <float> [#uses=1]
14 %5 = fsub float 1.000000e+00, %4 ; <float> [#uses=1]
17 %6 = fsub float 1.000000e+00, undef ; <float> [#uses=2]
18 %7 = fsub float %2, undef ; <float> [#uses=1]
19 %8 = fsub float 0.000000e+00, undef ; <float> [#uses=3]
20 %9 = fadd float %2, undef ; <float> [#uses=3]
[all …]
/external/llvm/test/CodeGen/Generic/
D2003-05-28-ManyArgs.ll21 %struct..s_annealing_sched = type { i32, float, float, float, float }
22 %struct..s_chan = type { i32, float, float, float, float }
23 …%struct..s_det_routing_arch = type { i32, float, float, float, i32, i32, i16, i16, i16, float, flo…
24 %struct..s_placer_opts = type { i32, float, i32, i32, i8*, i32, i32 }
25 %struct..s_router_opts = type { float, float, float, float, float, i32, i32, i32, i32 }
26 %struct..s_segment_inf = type { float, i32, i16, i16, float, float, i32, float, float }
27 %struct..s_switch_inf = type { i32, float, float, float, float }
44 … float, float, float, float, float, float, float, float, float, float } ; <{ i32, float, float, f…
50 …2, float, float, float, float, float, float, float, float, float, float }, { i32, float, float, fl…
56 …tr %struct..s_placer_opts, %struct..s_placer_opts* %placer_opts, i64 0, i32 1 ; <float*> [#uses=1]
[all …]
/external/llvm/test/Transforms/InstCombine/
Dminnum.ll3 declare float @llvm.minnum.f32(float, float) #0
4 declare float @llvm.minnum.v2f32(<2 x float>, <2 x float>) #0
5 declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #0
10 declare float @llvm.maxnum.f32(float, float) #0
13 ; CHECK-NEXT: ret float 1.000000e+00
14 define float @constant_fold_minnum_f32() #0 {
15 %x = call float @llvm.minnum.f32(float 1.0, float 2.0) #0
16 ret float %x
20 ; CHECK-NEXT: ret float 1.000000e+00
21 define float @constant_fold_minnum_f32_inv() #0 {
[all …]
Dmaxnum.ll3 declare float @llvm.maxnum.f32(float, float) #0
4 declare float @llvm.maxnum.v2f32(<2 x float>, <2 x float>) #0
5 declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #0
11 ; CHECK-NEXT: ret float 2.000000e+00
12 define float @constant_fold_maxnum_f32() #0 {
13 %x = call float @llvm.maxnum.f32(float 1.0, float 2.0) #0
14 ret float %x
18 ; CHECK-NEXT: ret float 2.000000e+00
19 define float @constant_fold_maxnum_f32_inv() #0 {
20 %x = call float @llvm.maxnum.f32(float 2.0, float 1.0) #0
[all …]
Dphi-merge-gep.ll8 define void @foo(float* %Ar, float* %Ai, i64 %As, float* %Cr, float* %Ci, i64 %Cs, i64 %n) nounwind…
10 %0 = getelementptr inbounds float, float* %Ar, i64 0 ; <float*> [#uses=1]
11 %1 = getelementptr inbounds float, float* %Ai, i64 0 ; <float*> [#uses=1]
13 %3 = getelementptr inbounds float, float* %Ar, i64 %2 ; <float*> [#uses=1]
15 %5 = getelementptr inbounds float, float* %Ai, i64 %4 ; <float*> [#uses=1]
18 %8 = getelementptr inbounds float, float* %Ar, i64 %7 ; <float*> [#uses=1]
21 %11 = getelementptr inbounds float, float* %Ai, i64 %10 ; <float*> [#uses=1]
22 %12 = getelementptr inbounds float, float* %Cr, i64 0 ; <float*> [#uses=1]
23 %13 = getelementptr inbounds float, float* %Ci, i64 0 ; <float*> [#uses=1]
25 %15 = getelementptr inbounds float, float* %Cr, i64 %14 ; <float*> [#uses=1]
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dfp-sqrt-01.ll5 declare float @llvm.sqrt.f32(float)
6 declare float @sqrtf(float)
9 define float @f1(float %val) {
13 %res = call float @llvm.sqrt.f32(float %val)
14 ret float %res
18 define float @f2(float *%ptr) {
22 %val = load float , float *%ptr
23 %res = call float @llvm.sqrt.f32(float %val)
24 ret float %res
28 define float @f3(float *%base) {
[all …]
/external/llvm/test/CodeGen/AArch64/
Dcallee-save.ll3 @var = global float 0.0
15 %val1 = load volatile float, float* @var
16 %val2 = load volatile float, float* @var
17 %val3 = load volatile float, float* @var
18 %val4 = load volatile float, float* @var
19 %val5 = load volatile float, float* @var
20 %val6 = load volatile float, float* @var
21 %val7 = load volatile float, float* @var
22 %val8 = load volatile float, float* @var
23 %val9 = load volatile float, float* @var
[all …]
/external/llvm/test/CodeGen/PowerPC/
DfloatPSA.ll10 …ne float @bar(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, floa…
12 %a.addr = alloca float, align 4
13 %b.addr = alloca float, align 4
14 %c.addr = alloca float, align 4
15 %d.addr = alloca float, align 4
16 %e.addr = alloca float, align 4
17 %f.addr = alloca float, align 4
18 %g.addr = alloca float, align 4
19 %h.addr = alloca float, align 4
20 %i.addr = alloca float, align 4
[all …]
Dunal-altivec2.ll6 define void @foo(float* noalias nocapture %x, float* noalias nocapture readonly %y) #0 {
15 %0 = getelementptr inbounds float, float* %y, i64 %index
16 %1 = bitcast float* %0 to <4 x float>*
17 %wide.load = load <4 x float>, <4 x float>* %1, align 4
18 %2 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load)
19 %3 = getelementptr inbounds float, float* %x, i64 %index
20 %4 = bitcast float* %3 to <4 x float>*
21 store <4 x float> %2, <4 x float>* %4, align 4
23 %5 = getelementptr inbounds float, float* %y, i64 %index.next
24 %6 = bitcast float* %5 to <4 x float>*
[all …]
/external/llvm/test/Transforms/Reassociate/
Dfast-basictest.ll4 define float @test1(float %arg) {
6 ; CHECK-NEXT: fsub fast float -0.000000e+00, %arg
7 ; CHECK-NEXT: ret float
9 %tmp1 = fsub fast float -1.200000e+01, %arg
10 %tmp2 = fadd fast float %tmp1, 1.200000e+01
11 ret float %tmp2
14 define float @test2(float %reg109, float %reg1111) {
16 ; CHECK-NEXT: fadd float %reg109, -3.000000e+01
17 ; CHECK-NEXT: fadd float %reg115, %reg1111
18 ; CHECK-NEXT: fadd float %reg116, 3.000000e+01
[all …]

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