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Searched refs:ISD (Results 1 – 25 of 157) sorted by relevance

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/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp42 if (getOpcode() < ISD::BUILTIN_OP_END) in getOperationName()
60 case ISD::DELETED_NODE: return "<<Deleted Node!>>"; in getOperationName()
62 case ISD::PREFETCH: return "Prefetch"; in getOperationName()
63 case ISD::ATOMIC_FENCE: return "AtomicFence"; in getOperationName()
64 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; in getOperationName()
65 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: return "AtomicCmpSwapWithSuccess"; in getOperationName()
66 case ISD::ATOMIC_SWAP: return "AtomicSwap"; in getOperationName()
67 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; in getOperationName()
68 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; in getOperationName()
69 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; in getOperationName()
[all …]
DLegalizeVectorOps.cpp201 if (Op.getOpcode() == ISD::LOAD) { in LegalizeOp()
203 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeOp()
204 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) in LegalizeOp()
229 } else if (Op.getOpcode() == ISD::STORE) { in LegalizeOp()
247 } else if (Op.getOpcode() == ISD::MSCATTER || Op.getOpcode() == ISD::MSTORE) in LegalizeOp()
261 case ISD::ADD: in LegalizeOp()
262 case ISD::SUB: in LegalizeOp()
263 case ISD::MUL: in LegalizeOp()
264 case ISD::SDIV: in LegalizeOp()
265 case ISD::UDIV: in LegalizeOp()
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DLegalizeIntegerTypes.cpp52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; in PromoteIntegerResult()
53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; in PromoteIntegerResult()
54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; in PromoteIntegerResult()
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; in PromoteIntegerResult()
56 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break; in PromoteIntegerResult()
57 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; in PromoteIntegerResult()
58 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; in PromoteIntegerResult()
59 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; in PromoteIntegerResult()
60 case ISD::CONVERT_RNDSAT: in PromoteIntegerResult()
62 case ISD::CTLZ_ZERO_UNDEF: in PromoteIntegerResult()
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DLegalizeDAG.cpp272 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) && in ExpandConstantFP()
286 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx, in ExpandConstantFP()
316 assert(ST->getAddressingMode() == ISD::UNINDEXED && in ExpandUnalignedStore()
333 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); in ExpandUnalignedStore()
375 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, in ExpandUnalignedStore()
377 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); in ExpandUnalignedStore()
387 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, in ExpandUnalignedStore()
399 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); in ExpandUnalignedStore()
416 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in ExpandUnalignedStore()
425 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, in ExpandUnalignedStore()
[all …]
DTargetLowering.cpp125 ISD::CondCode &CCCode, in softenSetCCOperands()
134 case ISD::SETEQ: in softenSetCCOperands()
135 case ISD::SETOEQ: in softenSetCCOperands()
139 case ISD::SETNE: in softenSetCCOperands()
140 case ISD::SETUNE: in softenSetCCOperands()
144 case ISD::SETGE: in softenSetCCOperands()
145 case ISD::SETOGE: in softenSetCCOperands()
149 case ISD::SETLT: in softenSetCCOperands()
150 case ISD::SETOLT: in softenSetCCOperands()
154 case ISD::SETLE: in softenSetCCOperands()
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DDAGCombiner.cpp136 if (N->getOpcode() == ISD::HANDLENODE) in AddToWorklist()
216 ISD::NodeType ExtType);
337 SDValue N3, ISD::CondCode CC,
339 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
573 if (Op.getOpcode() == ISD::FNEG) return 2; in isNegatibleForFree()
583 case ISD::ConstantFP: in isNegatibleForFree()
587 case ISD::FADD: in isNegatibleForFree()
593 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) in isNegatibleForFree()
603 case ISD::FSUB: in isNegatibleForFree()
610 case ISD::FMUL: in isNegatibleForFree()
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DLegalizeVectorTypes.cpp51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; in ScalarizeVectorResult()
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; in ScalarizeVectorResult()
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break; in ScalarizeVectorResult()
54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; in ScalarizeVectorResult()
55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; in ScalarizeVectorResult()
56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; in ScalarizeVectorResult()
57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break; in ScalarizeVectorResult()
58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; in ScalarizeVectorResult()
59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; in ScalarizeVectorResult()
60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break; in ScalarizeVectorResult()
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DLegalizeFloatTypes.cpp62 case ISD::Register: in SoftenFloatResult()
63 case ISD::CopyFromReg: in SoftenFloatResult()
64 case ISD::CopyToReg: in SoftenFloatResult()
70 case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break; in SoftenFloatResult()
71 case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N, ResNo); break; in SoftenFloatResult()
72 case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break; in SoftenFloatResult()
73 case ISD::ConstantFP: R = SoftenFloatRes_ConstantFP(N, ResNo); break; in SoftenFloatResult()
74 case ISD::EXTRACT_VECTOR_ELT: in SoftenFloatResult()
76 case ISD::FABS: R = SoftenFloatRes_FABS(N, ResNo); break; in SoftenFloatResult()
77 case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break; in SoftenFloatResult()
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/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp95 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getArithmeticInstrCost() local
96 assert(ISD && "Invalid opcode"); in getArithmeticInstrCost()
98 if (ISD == ISD::SDIV && in getArithmeticInstrCost()
119 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. in getArithmeticInstrCost()
121 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
122 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
123 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
124 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
129 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, in getArithmeticInstrCost()
135 { ISD::SHL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
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DX86IntrinsicsInfo.h259 X86_INTRINSIC_DATA(avx2_pmaxs_b, INTR_TYPE_2OP, ISD::SMAX, 0),
260 X86_INTRINSIC_DATA(avx2_pmaxs_d, INTR_TYPE_2OP, ISD::SMAX, 0),
261 X86_INTRINSIC_DATA(avx2_pmaxs_w, INTR_TYPE_2OP, ISD::SMAX, 0),
262 X86_INTRINSIC_DATA(avx2_pmaxu_b, INTR_TYPE_2OP, ISD::UMAX, 0),
263 X86_INTRINSIC_DATA(avx2_pmaxu_d, INTR_TYPE_2OP, ISD::UMAX, 0),
264 X86_INTRINSIC_DATA(avx2_pmaxu_w, INTR_TYPE_2OP, ISD::UMAX, 0),
265 X86_INTRINSIC_DATA(avx2_pmins_b, INTR_TYPE_2OP, ISD::SMIN, 0),
266 X86_INTRINSIC_DATA(avx2_pmins_d, INTR_TYPE_2OP, ISD::SMIN, 0),
267 X86_INTRINSIC_DATA(avx2_pmins_w, INTR_TYPE_2OP, ISD::SMIN, 0),
268 X86_INTRINSIC_DATA(avx2_pminu_b, INTR_TYPE_2OP, ISD::UMIN, 0),
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/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp51 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getCastInstrCost() local
52 assert(ISD && "Invalid opcode"); in getCastInstrCost()
57 { ISD::FP_ROUND, MVT::v2f64, 2 }, in getCastInstrCost()
58 { ISD::FP_EXTEND, MVT::v2f32, 2 }, in getCastInstrCost()
59 { ISD::FP_EXTEND, MVT::v4f32, 4 } in getCastInstrCost()
62 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND || in getCastInstrCost()
63 ISD == ISD::FP_EXTEND)) { in getCastInstrCost()
65 if (const auto *Entry = CostTableLookup(NEONFltDblTbl, ISD, LT.second)) in getCastInstrCost()
79 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
80 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
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DARMISelLowering.cpp91 setOperationAction(ISD::LOAD, VT, Promote); in addTypeForNEON()
92 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT); in addTypeForNEON()
94 setOperationAction(ISD::STORE, VT, Promote); in addTypeForNEON()
95 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT); in addTypeForNEON()
100 setOperationAction(ISD::SETCC, VT, Custom); in addTypeForNEON()
101 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
102 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
104 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in addTypeForNEON()
105 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in addTypeForNEON()
106 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
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/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp180 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getCastInstrCost() local
181 assert(ISD && "Invalid opcode"); in getCastInstrCost()
191 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, in getCastInstrCost()
192 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
193 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
194 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
197 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
198 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
199 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
200 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
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DAArch64ISelLowering.cpp112 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); in AArch64TargetLowering()
113 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); in AArch64TargetLowering()
114 setOperationAction(ISD::SETCC, MVT::i32, Custom); in AArch64TargetLowering()
115 setOperationAction(ISD::SETCC, MVT::i64, Custom); in AArch64TargetLowering()
116 setOperationAction(ISD::SETCC, MVT::f32, Custom); in AArch64TargetLowering()
117 setOperationAction(ISD::SETCC, MVT::f64, Custom); in AArch64TargetLowering()
118 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in AArch64TargetLowering()
119 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in AArch64TargetLowering()
120 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in AArch64TargetLowering()
121 setOperationAction(ISD::BR_CC, MVT::f32, Custom); in AArch64TargetLowering()
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/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom); in InitAMDILLowering()
111 setOperationAction(ISD::SUBE, VT, Expand); in InitAMDILLowering()
112 setOperationAction(ISD::SUBC, VT, Expand); in InitAMDILLowering()
113 setOperationAction(ISD::ADDE, VT, Expand); in InitAMDILLowering()
114 setOperationAction(ISD::ADDC, VT, Expand); in InitAMDILLowering()
115 setOperationAction(ISD::BRCOND, VT, Custom); in InitAMDILLowering()
116 setOperationAction(ISD::BR_JT, VT, Expand); in InitAMDILLowering()
117 setOperationAction(ISD::BRIND, VT, Expand); in InitAMDILLowering()
119 setOperationAction(ISD::SREM, VT, Expand); in InitAMDILLowering()
120 setOperationAction(ISD::SMUL_LOHI, VT, Expand); in InitAMDILLowering()
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DAMDGPUISelLowering.cpp31 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in AMDGPUTargetLowering()
35 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
36 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in AMDGPUTargetLowering()
37 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
39 setOperationAction(ISD::UDIV, MVT::i32, Expand); in AMDGPUTargetLowering()
40 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in AMDGPUTargetLowering()
41 setOperationAction(ISD::UREM, MVT::i32, Expand); in AMDGPUTargetLowering()
52 const SmallVectorImpl<ISD::InputArg> &Ins, in LowerFormalArguments()
68 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
89 case ISD::SDIV: return LowerSDIV(Op, DAG); in LowerOperation()
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/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp36 ISD::ArgFlagsTy ArgFlags, CCState &State) { in allocateStack()
68 setOperationAction(ISD::Constant, MVT::i32, Legal); in AMDGPUTargetLowering()
69 setOperationAction(ISD::Constant, MVT::i64, Legal); in AMDGPUTargetLowering()
70 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); in AMDGPUTargetLowering()
71 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); in AMDGPUTargetLowering()
73 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in AMDGPUTargetLowering()
74 setOperationAction(ISD::BRIND, MVT::Other, Expand); in AMDGPUTargetLowering()
77 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); in AMDGPUTargetLowering()
80 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in AMDGPUTargetLowering()
84 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
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DSIISelLowering.cpp69 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand); in SITargetLowering()
70 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand); in SITargetLowering()
71 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand); in SITargetLowering()
72 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand); in SITargetLowering()
74 setOperationAction(ISD::ADD, MVT::i32, Legal); in SITargetLowering()
75 setOperationAction(ISD::ADDC, MVT::i32, Legal); in SITargetLowering()
76 setOperationAction(ISD::ADDE, MVT::i32, Legal); in SITargetLowering()
77 setOperationAction(ISD::SUBC, MVT::i32, Legal); in SITargetLowering()
78 setOperationAction(ISD::SUBE, MVT::i32, Legal); in SITargetLowering()
80 setOperationAction(ISD::FSIN, MVT::f32, Custom); in SITargetLowering()
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DR600ISelLowering.cpp46 setCondCodeAction(ISD::SETO, MVT::f32, Expand); in R600TargetLowering()
47 setCondCodeAction(ISD::SETUO, MVT::f32, Expand); in R600TargetLowering()
48 setCondCodeAction(ISD::SETLT, MVT::f32, Expand); in R600TargetLowering()
49 setCondCodeAction(ISD::SETLE, MVT::f32, Expand); in R600TargetLowering()
50 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand); in R600TargetLowering()
51 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); in R600TargetLowering()
52 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); in R600TargetLowering()
53 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); in R600TargetLowering()
54 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); in R600TargetLowering()
55 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in R600TargetLowering()
[all …]
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp116 setOperationAction(ISD::GlobalAddress, MVTPtr, Custom); in WebAssemblyTargetLowering()
117 setOperationAction(ISD::ExternalSymbol, MVTPtr, Custom); in WebAssemblyTargetLowering()
118 setOperationAction(ISD::JumpTable, MVTPtr, Custom); in WebAssemblyTargetLowering()
122 setOperationAction(ISD::VASTART, MVT::Other, Custom); in WebAssemblyTargetLowering()
123 setOperationAction(ISD::VAARG, MVT::Other, Expand); in WebAssemblyTargetLowering()
124 setOperationAction(ISD::VACOPY, MVT::Other, Expand); in WebAssemblyTargetLowering()
125 setOperationAction(ISD::VAEND, MVT::Other, Expand); in WebAssemblyTargetLowering()
129 setOperationAction(ISD::ConstantFP, T, Legal); in WebAssemblyTargetLowering()
131 for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE, in WebAssemblyTargetLowering()
132 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) in WebAssemblyTargetLowering()
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/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp107 ISD::ArgFlagsTy ArgFlags, CCState &State);
112 ISD::ArgFlagsTy ArgFlags, CCState &State);
117 ISD::ArgFlagsTy ArgFlags, CCState &State);
122 ISD::ArgFlagsTy ArgFlags, CCState &State);
127 ISD::ArgFlagsTy ArgFlags, CCState &State);
132 ISD::ArgFlagsTy ArgFlags, CCState &State);
137 ISD::ArgFlagsTy ArgFlags, CCState &State);
142 ISD::ArgFlagsTy ArgFlags, CCState &State);
147 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_Hexagon_VarArg()
221 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_Hexagon()
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/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp77 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in MSP430TargetLowering()
78 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in MSP430TargetLowering()
81 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
82 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
83 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
84 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in MSP430TargetLowering()
85 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); in MSP430TargetLowering()
91 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
92 setOperationAction(ISD::SHL, MVT::i8, Custom); in MSP430TargetLowering()
93 setOperationAction(ISD::SRL, MVT::i8, Custom); in MSP430TargetLowering()
[all …]
/external/llvm/include/llvm/CodeGen/
DBasicTTIImpl.h183 return TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || in shouldBuildLookupTables()
184 TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other); in shouldBuildLookupTables()
191 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); in haveFastSqrt()
293 int ISD = TLI->InstructionOpcodeToISD(Opcode); variable
294 assert(ISD && "Invalid opcode");
303 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
309 if (!TLI->isOperationExpand(ISD, LT.second)) {
340 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getCastInstrCost() local
341 assert(ISD && "Invalid opcode"); in getCastInstrCost()
364 TLI->isOperationLegalOrPromote(ISD, DstLT.second)) in getCastInstrCost()
[all …]
DSelectionDAGNodes.h66 namespace ISD {
445 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
451 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
455 bool isUndef() const { return NodeType == ISD::UNDEF; }
463 return (NodeType == ISD::INTRINSIC_W_CHAIN ||
464 NodeType == ISD::INTRINSIC_VOID) && ((SubclassData >> 13) & 1);
710 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
1023 case ISD::SDIV:
1024 case ISD::UDIV:
1025 case ISD::SRA:
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/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp103 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in BPFTargetLowering()
104 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in BPFTargetLowering()
105 setOperationAction(ISD::BRIND, MVT::Other, Expand); in BPFTargetLowering()
106 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in BPFTargetLowering()
107 setOperationAction(ISD::SETCC, MVT::i64, Expand); in BPFTargetLowering()
108 setOperationAction(ISD::SELECT, MVT::i64, Expand); in BPFTargetLowering()
109 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in BPFTargetLowering()
111 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); in BPFTargetLowering()
113 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); in BPFTargetLowering()
114 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); in BPFTargetLowering()
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