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Searched refs:NewOpc (Results 1 – 25 of 33) sorted by relevance

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/external/llvm/lib/Target/X86/Disassembler/
DX86Disassembler.cpp345 unsigned NewOpc; in translateImmediate() local
348 case X86::CMPPDrmi: NewOpc = X86::CMPPDrmi_alt; break; in translateImmediate()
349 case X86::CMPPDrri: NewOpc = X86::CMPPDrri_alt; break; in translateImmediate()
350 case X86::CMPPSrmi: NewOpc = X86::CMPPSrmi_alt; break; in translateImmediate()
351 case X86::CMPPSrri: NewOpc = X86::CMPPSrri_alt; break; in translateImmediate()
352 case X86::CMPSDrm: NewOpc = X86::CMPSDrm_alt; break; in translateImmediate()
353 case X86::CMPSDrr: NewOpc = X86::CMPSDrr_alt; break; in translateImmediate()
354 case X86::CMPSSrm: NewOpc = X86::CMPSSrm_alt; break; in translateImmediate()
355 case X86::CMPSSrr: NewOpc = X86::CMPSSrr_alt; break; in translateImmediate()
356 case X86::VPCOMBri: NewOpc = X86::VPCOMBri_alt; break; in translateImmediate()
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/external/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp1201 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); in MergeBaseUpdateLSMultiple() local
1202 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) in MergeBaseUpdateLSMultiple()
1301 unsigned NewOpc; in MergeBaseUpdateLoadStore() local
1303 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add); in MergeBaseUpdateLoadStore()
1305 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub); in MergeBaseUpdateLoadStore()
1309 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add); in MergeBaseUpdateLoadStore()
1311 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub); in MergeBaseUpdateLoadStore()
1326 BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) in MergeBaseUpdateLoadStore()
1335 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { in MergeBaseUpdateLoadStore()
1336 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
[all …]
DThumb2InstrInfo.cpp497 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in rewriteT2FrameIndex() local
498 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
531 unsigned NewOpc = Opcode; in rewriteT2FrameIndex() local
541 NewOpc = immediateOffsetOpcode(Opcode); in rewriteT2FrameIndex()
553 NewOpc = negativeOffsetOpcode(Opcode); in rewriteT2FrameIndex()
558 NewOpc = positiveOffsetOpcode(Opcode); in rewriteT2FrameIndex()
585 if (NewOpc != Opcode) in rewriteT2FrameIndex()
586 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
619 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc))); in rewriteT2FrameIndex()
DARMConstantIslandPass.cpp1842 unsigned NewOpc = 0; in optimizeThumb2Instructions() local
1849 NewOpc = ARM::tLEApcrel; in optimizeThumb2Instructions()
1856 NewOpc = ARM::tLDRpci; in optimizeThumb2Instructions()
1863 if (!NewOpc) in optimizeThumb2Instructions()
1876 U.MI->setDesc(TII->get(NewOpc)); in optimizeThumb2Instructions()
1901 unsigned NewOpc = 0; in optimizeThumb2Branches() local
1907 NewOpc = ARM::tB; in optimizeThumb2Branches()
1912 NewOpc = ARM::tBcc; in optimizeThumb2Branches()
1918 if (NewOpc) { in optimizeThumb2Branches()
1923 Br.MI->setDesc(TII->get(NewOpc)); in optimizeThumb2Branches()
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DARMExpandPseudoInsts.cpp848 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; in ExpandMI() local
849 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), in ExpandMI()
887 unsigned NewOpc; in ExpandMI() local
889 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; in ExpandMI()
890 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; in ExpandMI()
891 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; in ExpandMI()
892 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; in ExpandMI()
895 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), in ExpandMI()
1131 unsigned NewOpc = ARM::VLDMDIA; in ExpandMI() local
1133 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMI()
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DThumbRegisterInfo.cpp398 unsigned NewOpc = convertToNonSPOpcode(Opcode); in rewriteFrameIndex() local
399 if (NewOpc != Opcode && FrameReg != ARM::SP) in rewriteFrameIndex()
400 MI.setDesc(TII.get(NewOpc)); in rewriteFrameIndex()
DARMISelLowering.cpp2825 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) in LowerINTRINSIC_WO_CHAIN() local
2827 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
2832 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm) in LowerINTRINSIC_WO_CHAIN() local
2834 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
2841 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu) in LowerINTRINSIC_WO_CHAIN() local
2843 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
2850 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins) in LowerINTRINSIC_WO_CHAIN() local
2852 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
2855 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins) in LowerINTRINSIC_WO_CHAIN() local
2857 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
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/external/llvm/lib/Target/X86/
DX86MCInstLower.cpp478 unsigned NewOpc; in Lower() local
481 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break; in Lower()
482 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; in Lower()
483 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; in Lower()
484 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; in Lower()
485 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; in Lower()
486 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; in Lower()
487 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; in Lower()
488 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; in Lower()
489 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break; in Lower()
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DX86InstrInfo.cpp5132 unsigned NewOpc; in optimizeCompareInstr() local
5134 NewOpc = GetCondBranchFromCond(NewCC); in optimizeCompareInstr()
5136 NewOpc = getSETFromCond(NewCC, HasMemoryOperand); in optimizeCompareInstr()
5139 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(), in optimizeCompareInstr()
5146 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc)); in optimizeCompareInstr()
5933 unsigned NewOpc = 0; in foldMemoryOperandImpl() local
5937 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; in foldMemoryOperandImpl()
5938 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; in foldMemoryOperandImpl()
5939 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break; in foldMemoryOperandImpl()
5940 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break; in foldMemoryOperandImpl()
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/external/llvm/lib/Target/Hexagon/
DHexagonGenPredicate.cpp370 unsigned NewOpc = getPredForm(Opc); in convertToPredForm() local
372 if (NewOpc == 0) { in convertToPredForm()
375 NewOpc = Hexagon::C2_not; in convertToPredForm()
378 NewOpc = TargetOpcode::COPY; in convertToPredForm()
405 MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R); in convertToPredForm()
/external/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp301 unsigned NewOpc = getTransformOpcode(OldOpc); in transformInstruction() local
302 assert(OldOpc != NewOpc && "transform an instruction to itself?!"); in transformInstruction()
356 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(NewOpc), Dst) in transformInstruction()
DAArch64InstrInfo.cpp840 unsigned NewOpc = convertFlagSettingOpcode(CmpInstr); in optimizeCompareInstr() local
841 if (NewOpc == Opc) in optimizeCompareInstr()
843 const MCInstrDesc &MCID = get(NewOpc); in optimizeCompareInstr()
873 unsigned NewOpc = MI->getOpcode(); in optimizeCompareInstr() local
886 case AArch64::ADDWrr: NewOpc = AArch64::ADDSWrr; break; in optimizeCompareInstr()
887 case AArch64::ADDWri: NewOpc = AArch64::ADDSWri; break; in optimizeCompareInstr()
888 case AArch64::ADDXrr: NewOpc = AArch64::ADDSXrr; break; in optimizeCompareInstr()
889 case AArch64::ADDXri: NewOpc = AArch64::ADDSXri; break; in optimizeCompareInstr()
890 case AArch64::ADCWr: NewOpc = AArch64::ADCSWr; break; in optimizeCompareInstr()
891 case AArch64::ADCXr: NewOpc = AArch64::ADCSXr; break; in optimizeCompareInstr()
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DAArch64LoadStoreOptimizer.cpp591 unsigned NewOpc = getMatchingPairOpcode(Opc); in mergePairedInsns() local
632 TII->get(NewOpc)) in mergePairedInsns()
726 TII->get(NewOpc)) in mergePairedInsns()
737 TII->get(NewOpc)) in mergePairedInsns()
1062 unsigned NewOpc = IsPreIdx ? getPreIndexedOpcode(I->getOpcode()) in mergeUpdateInsn() local
1067 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc)) in mergeUpdateInsn()
1075 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc)) in mergeUpdateInsn()
DAArch64ISelLowering.cpp2149 unsigned NewOpc = 0; in LowerMUL() local
2154 NewOpc = AArch64ISD::SMULL; in LowerMUL()
2159 NewOpc = AArch64ISD::UMULL; in LowerMUL()
2164 NewOpc = AArch64ISD::SMULL; in LowerMUL()
2167 NewOpc = AArch64ISD::UMULL; in LowerMUL()
2171 NewOpc = AArch64ISD::UMULL; in LowerMUL()
2176 if (!NewOpc) { in LowerMUL()
2195 return DAG.getNode(NewOpc, DL, VT, Op0, Op1); in LowerMUL()
2204 DAG.getNode(NewOpc, DL, VT, in LowerMUL()
2206 DAG.getNode(NewOpc, DL, VT, in LowerMUL()
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/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp2410 unsigned NewOpc; in processInstruction() local
2413 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break; in processInstruction()
2414 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; in processInstruction()
2415 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; in processInstruction()
2416 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; in processInstruction()
2417 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; in processInstruction()
2418 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; in processInstruction()
2419 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; in processInstruction()
2420 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; in processInstruction()
2421 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break; in processInstruction()
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/external/llvm/lib/Target/Mips/
DMipsInstrInfo.cpp278 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, in genInstrWithNewOpc() argument
281 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc)); in genInstrWithNewOpc()
DMipsSEInstrInfo.h91 unsigned NewOpc) const;
DMipsSEISelLowering.h68 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
DMipsInstrInfo.h125 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
DMipsLongBranch.cpp219 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); in replaceBranch() local
220 const MCInstrDesc &NewDesc = TII->get(NewOpc); in replaceBranch()
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelDAGToDAG.cpp166 unsigned int NewOpc = AMDGPU::COPY; in Select() local
168 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, TFI); in Select()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp474 unsigned NewOpc; in PromoteFP_TO_INT() local
479 NewOpc = ISD::FP_TO_SINT; in PromoteFP_TO_INT()
483 NewOpc = ISD::FP_TO_UINT; in PromoteFP_TO_INT()
489 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0)); in PromoteFP_TO_INT()
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp476 int NewOpc; in commuteOpcode() local
479 NewOpc = AMDGPU::getCommuteRev(Opcode); in commuteOpcode()
480 if (NewOpc != -1) in commuteOpcode()
482 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1; in commuteOpcode()
485 NewOpc = AMDGPU::getCommuteOrig(Opcode); in commuteOpcode()
486 if (NewOpc != -1) in commuteOpcode()
488 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1; in commuteOpcode()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp7844 unsigned NewOpc; in processInstruction() local
7847 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; in processInstruction()
7848 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; in processInstruction()
7849 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; in processInstruction()
7853 TmpInst.setOpcode(NewOpc); in processInstruction()
8326 unsigned NewOpc; in processInstruction() local
8329 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; in processInstruction()
8330 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; in processInstruction()
8331 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; in processInstruction()
8332 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; in processInstruction()
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/external/llvm/lib/CodeGen/
DMachineLICM.cpp1175 unsigned NewOpc = in ExtractHoistableLoad() local
1180 if (NewOpc == 0) return nullptr; in ExtractHoistableLoad()
1181 const MCInstrDesc &MID = TII->get(NewOpc); in ExtractHoistableLoad()

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