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Searched refs:DefIdx (Results 1 – 25 of 31) sorted by relevance

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/external/llvm/include/llvm/MC/
DMCInstrItineraries.h186 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding() argument
190 if ((FirstDefIdx + DefIdx) >= LastDefIdx) in hasPipelineForwarding()
192 if (Forwardings[FirstDefIdx + DefIdx] == 0) in hasPipelineForwarding()
200 return Forwardings[FirstDefIdx + DefIdx] == in hasPipelineForwarding()
207 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency() argument
212 int DefCycle = getOperandCycle(DefClass, DefIdx); in getOperandLatency()
222 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
DMCSubtargetInfo.h128 unsigned DefIdx) const { in getWriteLatencyEntry() argument
129 assert(DefIdx < SC->NumWriteLatencyEntries && in getWriteLatencyEntry()
132 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx]; in getWriteLatencyEntry()
/external/llvm/lib/CodeGen/
DTargetSchedule.cpp128 unsigned DefIdx = 0; in findDefIdx() local
132 ++DefIdx; in findDefIdx()
134 return DefIdx; in findDefIdx()
188 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
189 if (DefIdx < SCDesc->NumWriteLatencyEntries) { in computeOperandLatency()
192 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeOperandLatency()
214 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for " in computeOperandLatency()
228 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
229 DefIdx != DefEnd; ++DefIdx) { in computeInstrLatency()
232 STI->getWriteLatencyEntry(&SCDesc, DefIdx); in computeInstrLatency()
DTargetInstrInfo.cpp983 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
993 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
995 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1059 unsigned DefIdx) const { in hasLowDefLatency()
1065 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
1073 const MachineInstr *DefMI, unsigned DefIdx, in getOperandLatency() argument
1077 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1110 const MachineInstr *DefMI, unsigned DefIdx, in computeOperandLatency() argument
1121 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx); in computeOperandLatency()
1124 OperLatency = ItinData->getOperandCycle(DefClass, DefIdx); in computeOperandLatency()
[all …]
DPeepholeOptimizer.cpp296 unsigned DefIdx; member in __anone8ceb28c0111::ValueTracker
354 : Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg), in ValueTracker()
358 DefIdx = MRI.def_begin(Reg).getOperandNo(); in ValueTracker()
369 ValueTracker(const MachineInstr &MI, unsigned DefIdx, unsigned DefSubReg, in ValueTracker() argument
373 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg), in ValueTracker()
375 assert(DefIdx < Def->getDesc().getNumDefs() && in ValueTracker()
376 Def->getOperand(DefIdx).isReg() && "Invalid definition"); in ValueTracker()
377 Reg = Def->getOperand(DefIdx).getReg(); in ValueTracker()
1679 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromCopy()
1698 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromBitcast()
[all …]
DLiveRangeEdit.cpp126 SlotIndex DefIdx; in canRematerializeAt() local
128 DefIdx = LIS.getInstructionIndex(RM.OrigMI); in canRematerializeAt()
130 DefIdx = RM.ParentVNI->def; in canRematerializeAt()
131 RM.OrigMI = LIS.getInstructionFromIndex(DefIdx); in canRematerializeAt()
140 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
DLiveRangeCalc.cpp46 SlotIndex DefIdx = in createDeadDef() local
50 LR.createDeadDef(DefIdx, Alloc); in createDeadDef()
179 unsigned DefIdx; in extendToUses() local
182 else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) { in extendToUses()
185 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber(); in extendToUses()
DMachineVerifier.cpp907 unsigned DefIdx; in visitMachineOperand() local
909 MI->isRegTiedToDefOperand(MONum, &DefIdx) && in visitMachineOperand()
910 Reg != MI->getOperand(DefIdx).getReg()) in visitMachineOperand()
1159 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI); in checkLiveness() local
1160 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber()); in checkLiveness()
1163 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) { in checkLiveness()
1165 if (VNI->def != DefIdx) { in checkLiveness()
1168 << DefIdx << " in " << LI << '\n'; in checkLiveness()
1172 errs() << DefIdx << " is not live in " << LI << '\n'; in checkLiveness()
1176 LiveQueryResult LRQ = LI.Query(DefIdx); in checkLiveness()
DMachineInstr.cpp815 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand() local
816 if (DefIdx != -1) in addOperand()
817 tieOperands(DefIdx, OpNo); in addOperand()
1098 unsigned DefIdx; in getRegClassConstraint() local
1099 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
1100 OpIdx = DefIdx; in getRegClassConstraint()
1291 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands() argument
1292 MachineOperand &DefMO = getOperand(DefIdx); in tieOperands()
1299 if (DefIdx < TiedMax) in tieOperands()
1300 UseMO.TiedTo = DefIdx + 1; in tieOperands()
DTargetRegisterInfo.cpp306 unsigned SrcIdx, DefIdx; in shareSameRegisterFile() local
309 SrcIdx, DefIdx) != nullptr; in shareSameRegisterFile()
DRegisterCoalescer.cpp661 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); in removeCopyByCommutingDef() local
662 assert(DefIdx != -1); in removeCopyByCommutingDef()
664 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) in removeCopyByCommutingDef()
770 SlotIndex DefIdx = UseIdx.getRegSlot(); in removeCopyByCommutingDef() local
771 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx); in removeCopyByCommutingDef()
774 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI); in removeCopyByCommutingDef()
775 assert(DVNI->def == DefIdx); in removeCopyByCommutingDef()
778 VNInfo *SubDVNI = S.getVNInfoAt(DefIdx); in removeCopyByCommutingDef()
DInlineSpiller.cpp916 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewVReg, RM, in reMaterializeFor() local
918 (void)DefIdx; in reMaterializeFor()
919 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t' in reMaterializeFor()
920 << *LIS.getInstructionFromIndex(DefIdx)); in reMaterializeFor()
DRegAllocFast.cpp743 unsigned DefIdx = 0; in handleThroughOperands() local
744 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue; in handleThroughOperands()
746 << DefIdx << ".\n"); in handleThroughOperands()
DMachineLICM.cpp181 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
976 unsigned DefIdx, unsigned Reg) const { in HasHighOperandLatency() argument
993 if (TII->hasHighOperandLatency(SchedModel, MRI, &MI, DefIdx, &UseMI, i)) in HasHighOperandLatency()
/external/llvm/lib/Target/ARM/
DARMBaseInstrInfo.h56 const MachineInstr &MI, unsigned DefIdx,
69 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
85 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
285 const MachineInstr *DefMI, unsigned DefIdx,
289 SDNode *DefNode, unsigned DefIdx,
311 unsigned DefIdx, unsigned DefAlign) const;
315 unsigned DefIdx, unsigned DefAlign) const;
326 unsigned DefIdx, unsigned DefAlign,
341 const MachineInstr *DefMI, unsigned DefIdx,
346 unsigned DefIdx) const override;
DARMBaseInstrInfo.cpp3154 unsigned DefIdx, unsigned DefAlign) const { in getVLDMDefCycle() argument
3155 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getVLDMDefCycle()
3158 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
3195 unsigned DefIdx, unsigned DefAlign) const { in getLDMDefCycle() argument
3196 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getLDMDefCycle()
3199 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
3298 unsigned DefIdx, unsigned DefAlign, in getOperandLatency() argument
3304 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) in getOperandLatency()
3305 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
3314 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
[all …]
/external/llvm/include/llvm/Target/
DTargetInstrInfo.h379 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
397 getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
417 getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
891 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs() argument
905 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregLikeInputs() argument
919 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, in getInsertSubregLikeInputs() argument
1153 SDNode *DefNode, unsigned DefIdx,
1165 const MachineInstr *DefMI, unsigned DefIdx,
1172 const MachineInstr *DefMI, unsigned DefIdx,
1206 const MachineInstr *DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
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/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h120 const MachineInstr *DefMI, unsigned DefIdx,
124 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
126 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
132 unsigned DefIdx) const override { in hasLowDefLatency() argument
DPPCVSXSwapRemoval.cpp617 int DefIdx = SwapMap[DefMI]; in formWebs() local
618 (void)EC->unionSets(SwapVector[DefIdx].VSEId, in formWebs()
621 DEBUG(dbgs() << format("Unioning %d with %d\n", SwapVector[DefIdx].VSEId, in formWebs()
695 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
697 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad || in recordUnoptimizableWebs()
698 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
704 DEBUG(dbgs() << " def " << DefIdx << ": "); in recordUnoptimizableWebs()
751 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
752 SwapVector[DefIdx].WillRemove = 1; in markSwapsForRemoval()
/external/llvm/lib/MC/MCDisassembler/
DDisassembler.cpp203 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; in getLatency() local
204 DefIdx != DefEnd; ++DefIdx) { in getLatency()
207 DefIdx); in getLatency()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.h131 unsigned DefIdx; variable
149 return DefIdx-1; in GetIdx()
DScheduleDAGSDNodes.cpp554 DefIdx = 0; in InitNodeNumDefs()
560 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) { in RegDefIter()
568 for (;DefIdx < NodeNumDefs; ++DefIdx) { in Advance()
569 if (!Node->hasAnyUseOfValue(DefIdx)) in Advance()
571 ValueType = Node->getSimpleValueType(DefIdx); in Advance()
572 ++DefIdx; in Advance()
634 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency() local
638 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in computeOperandLatency()
/external/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp206 unsigned DefIdx = 0; in SelectInlineAsm() local
210 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx)) in SelectInlineAsm()
211 IsTiedToChangedOp = OpChanged[DefIdx]; in SelectInlineAsm()
297 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx); in SelectInlineAsm()
/external/llvm/include/llvm/CodeGen/
DTargetSchedule.h184 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
/external/llvm/lib/CodeGen/MIRParser/
DMIParser.cpp887 unsigned DefIdx = Operands[I].TiedDefIdx.getValue(); in assignRegisterTies() local
888 if (DefIdx >= E) in assignRegisterTies()
891 Twine(DefIdx) + "'; instruction has only ") + in assignRegisterTies()
893 const auto &DefOperand = Operands[DefIdx].Operand; in assignRegisterTies()
898 Twine(DefIdx) + "'; the operand #" + Twine(DefIdx) + in assignRegisterTies()
902 if (TiedPair.first == DefIdx) in assignRegisterTies()
904 Twine("the tied-def operand #") + Twine(DefIdx) + in assignRegisterTies()
907 TiedRegisterPairs.push_back(std::make_pair(DefIdx, I)); in assignRegisterTies()

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