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Searched refs:isPredicated (Results 1 – 25 of 47) sorted by relevance

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/external/mesa3d/src/gallium/drivers/radeon/
DR600InstrInfo.cpp207 if(!isPredicated(LastInst)) { in AnalyzeBranch()
231 isPredicated(SecondLastInst) && in AnalyzeBranch()
233 !isPredicated(LastInst)) { in AnalyzeBranch()
314 if (isPredicated(I)) { in RemoveBranch()
332 if (isPredicated(I)) { in RemoveBranch()
343 R600InstrInfo::isPredicated(const MachineInstr *MI) const in isPredicated() function in R600InstrInfo
DR600InstrInfo.h75 bool isPredicated(const MachineInstr *MI) const;
DAMDGPUInstrInfo.h116 bool isPredicated(const MachineInstr *MI) const;
DAMDGPUInstrInfo.cpp209 bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const { in isPredicated() function in AMDGPUInstrInfo
/external/llvm/lib/Target/Hexagon/
DHexagonIsetDx.td32 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isBr…
53 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicated…
93 let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, hasSideEffects = 0, hasN…
122 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, isBran…
211 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, mayLoad = 1,…
409 let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, hasSideEffects = 0, ha…
536 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPr…
547 let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opNewVal…
599 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isBranch = 1, isIndirectBra…
609 let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, h…
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DHexagonVLIWPacketizer.cpp441 if (!HII->isPredicated(MI)) in getPredicateSense()
573 if (HII->isPredicated(PacketMI)) { in canPromoteToNewValueStore()
574 if (!HII->isPredicated(MI)) in canPromoteToNewValueStore()
796 if (!HII->isPredicated(I)) in restrictingDepExistInPacket()
824 assert(QII->isPredicated(MI) && "Must be predicated instruction"); in getPredicatedRegister()
1048 if (HII->isPredicated(I) || HII->isPredicated(J)) in hasDeadDependence()
1088 if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI)) in hasControlDependence()
1278 if (HII->isPredicated(I) && HII->isPredicated(J) && in isLegalToPacketizeTogether()
DHexagonInstrInfo.h186 bool isPredicated(const MachineInstr *MI) const override;
308 bool isPredicated(unsigned Opcode) const;
DHexagonInstrFormatsV4.td67 bits<1> isPredicated = 0;
68 let TSFlags{6} = isPredicated;
DHexagonExpandCondsets.cpp424 bool Predicated = HII->isPredicated(MI); in addInstrToLiveness()
751 if (HII->isPredicated(MI) || !HII->isPredicable(MI)) in isPredicable()
787 if (PredValid && HII->isPredicated(MI)) { in getReachingDefForPred()
948 if (!HII->isPredicated(MI)) in renameInRange()
1017 if (PredValid && HII->isPredicated(MI) && MI->readsRegister(PredR)) in predicate()
1124 if (HII->isPredicated(MI)) in removeImplicitUses()
DHexagon.td200 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
208 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
DHexagonInstrInfo.cpp503 if (Term != MBB.end() && isPredicated(Term) && in InsertBranch()
1038 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const { in isPredicated() function in HexagonInstrInfo
1489 return (MI->isBranch() && isPredicated(MI)) || in isCondInst()
1494 (MI->mayStore() && isPredicated(MI) && !isNewValueStore(MI) && in isCondInst()
1560 if (!MI->getDesc().mayLoad() || !isPredicated(MI)) in isConditionalLoad()
1767 (isPredicated(MI) && isPredicatedNew(MI))) in isDotNewInst()
2102 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode); in isNewValueJump()
2134 assert(isPredicated(MI)); in isPredicatedNew()
2141 assert(isPredicated(Opcode)); in isPredicatedNew()
2162 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const { in isPredicated() function in HexagonInstrInfo
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DHexagonPeephole.cpp246 if (QII->isPredicated(MI)) { in runOnMachineFunction()
DHexagonInstrFormats.td115 bits<1> isPredicated = 0;
116 let TSFlags{8} = isPredicated;
194 let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
/external/llvm/lib/CodeGen/
DCriticalAntiDepBreaker.cpp168 TII->isPredicated(MI); in PrescanInstruction()
244 if (!TII->isPredicated(MI)) { in ScanInstruction()
588 if (MI->isCall() || MI->hasExtraDefRegAllocReq() || TII->isPredicated(MI)) in BreakAntiDependencies()
DIfConversion.cpp681 bool isPredicated = TII->isPredicated(I); in ScanInstructions() local
688 if (!isPredicated) { in ScanInstructions()
703 if (BBI.ClobbersPred && !isPredicated) { in ScanInstructions()
1555 if (I->isDebugValue() || TII->isPredicated(I)) in PredicateBlock()
1611 if (!TII->isPredicated(I) && !MI->isDebugValue()) { in CopyAndPredicateBlock()
DTargetSchedule.cpp285 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI)) in computeOutputLatency()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUInstrInfo.h125 bool isPredicated(const MachineInstr *MI) const override;
DR600InstrInfo.h171 bool isPredicated(const MachineInstr *MI) const override;
DAMDGPUInstrInfo.cpp228 bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const { in isPredicated() function in AMDGPUInstrInfo
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCChecker.cpp67 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && isPredicateRegister(R)) { in init()
289 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) || in checkBranches()
DHexagonMCCodeEmitter.cpp145 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) in EncodeSingleInstruction()
148 assert(HexagonMCInstrInfo::isPredicated(MCII, HMB) && in EncodeSingleInstruction()
DHexagonMCInstrInfo.h242 bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h233 bool isPredicated(const MachineInstr *MI) const override;
/external/llvm/lib/Target/ARM/
DARMBaseInstrInfo.cpp292 while (isPredicated(I) || I->isTerminator() || I->isDebugValue()) { in AnalyzeBranch()
325 CantAnalyze = !isPredicated(I); in AnalyzeBranch()
333 if (!isPredicated(I) && in AnalyzeBranch()
441 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const { in isPredicated() function in ARMBaseInstrInfo
2398 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) { in optimizeCompareInstr()
2406 isPredicated(PotentialAND)) in optimizeCompareInstr()
2474 if (isPredicated(MI)) in optimizeCompareInstr()
2621 assert(!isPredicated(MI) && "Can't use flags from predicated instruction"); in optimizeCompareInstr()
4155 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI)) in getExecutionDomain()
4160 if (Subtarget.isCortexA9() && !isPredicated(MI) && in getExecutionDomain()
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/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp167 return !isPredicated(MI); in isUnpredicatedTerminator()

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