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Searched refs:isRegMask (Results 1 – 25 of 33) sorted by relevance

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/external/llvm/lib/CodeGen/
DLivePhysRegs.cpp54 } else if (O->isRegMask()) in stepBackward()
91 } else if (O->isRegMask()) in stepForward()
DDeadMachineInstructionElim.cpp150 } else if (MO.isRegMask()) { in runOnMachineFunction()
DRegisterScavenging.cpp112 if (MO.isRegMask()) { in determineKillsAndDefs()
314 if (MO.isRegMask()) in findSurvivorReg()
DCriticalAntiDepBreaker.cpp250 if (MO.isRegMask()) in ScanInstruction()
348 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg)) in isNewRegClobberedByRefs()
DMachineCSE.cpp191 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) in isPhysDefTriviallyDead()
318 if (MO.isRegMask()) in PhysRegDefsReach()
DMachineInstrBundle.cpp303 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) { in analyzePhysReg()
DMachineCopyPropagation.cpp235 if (MO.isRegMask()) in CopyPropagateBlock()
DShrinkWrap.cpp238 } else if (MO.isRegMask()) { in INITIALIZE_PASS_DEPENDENCY()
DMachineInstr.cpp767 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() || in addOperand()
1239 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg)) in findRegisterDefOperandIdx()
1554 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask()) in copyImplicitOps()
1968 if (MO.isRegMask()) { in setPhysRegsDeadExcept()
DVirtRegMap.cpp366 if (MO.isRegMask()) in rewrite()
DEarlyIfConversion.cpp230 if (MO.isRegMask()) { in canSpeculateInstrs()
DLiveIntervalAnalysis.cpp237 if (!MO.isRegMask()) in computeRegMasks()
961 if (MO.isRegMask()) in updateAllRanges()
DBranchFolding.cpp1677 if (MO.isRegMask()) in findHoistingInsertPosAndDeps()
1788 if (MO.isRegMask()) { in HoistCommonCodeInSuccs()
DLiveVariables.cpp517 if (MO.isRegMask()) { in runOnInstr()
DRegAllocFast.cpp922 if (MO.isRegMask()) { in AllocateBasicBlock()
DMachineLICM.cpp371 if (MO.isRegMask()) { in ProcessMI()
DPeepholeOptimizer.cpp1554 } else if (Op.isRegMask()) { in runOnMachineFunction()
/external/llvm/lib/Target/X86/
DX86VZeroUpper.cpp128 if (MI->isCall() && MO.isRegMask() && !clobbersAllYmmRegs(MO)) in hasYmmReg()
146 if (!MO.isRegMask()) in callClobbersAnyYmmReg()
/external/llvm/lib/Target/AArch64/
DAArch64A57FPLoadBalancing.cpp510 if (J.isRegMask()) in scavengeRegister()
574 } else if (U.isRegMask()) { in colorChain()
709 } else if (MO.isRegMask()) { in maybeKillChain()
DAArch64CollectLOH.cpp325 if (!MO.isRegMask()) in initReachingDef()
DAArch64LoadStoreOptimizer.cpp809 if (MO.isRegMask()) in trackRegDefsUses()
/external/llvm/include/llvm/CodeGen/
DMachineOperand.h254 bool isRegMask() const { return OpKind == MO_RegisterMask; } in isRegMask() function
489 assert(isRegMask() && "Wrong MachineOperand accessor"); in getRegMask()
/external/llvm/lib/Target/PowerPC/
DPPCCTRLoops.cpp596 } else if (MO.isRegMask()) { in clobbersCTR()
/external/llvm/lib/Target/ARM/
DThumbRegisterInfo.cpp475 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) { in saveScavengerRegister()
/external/llvm/lib/CodeGen/MIRParser/
DMIRParser.cpp408 if (!MO.isRegMask()) in inferRegisterInfo()

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