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Searched refs:v32i32 (Results 1 – 12 of 12) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DMachineValueType.h92 v32i32 = 43, // 32 x i32 enumerator
266 SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 || in is1024BitVector()
340 case v32i32: in getVectorElementType()
380 case v32i32: in getVectorNumElements()
499 case v32i32: in getSizeInBits()
622 if (NumElements == 32) return MVT::v32i32; in getVectorVT()
DValueTypes.td69 def v32i32 : ValueType<1024,43>; // 32 x i32 vector value
/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV60.td63 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))),
64 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_loreg)) >,
67 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))),
68 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_hireg)) >,
71 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))),
72 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
76 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))),
77 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
122 def : Pat <(v1024i1 (bitconvert (v32i32 VectorRegs128B:$src1))),
123 (v1024i1 (V6_vandvrt_128B(v32i32 VectorRegs128B:$src1),
[all …]
DHexagonISelLowering.cpp203 if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_Hexagon_VarArg()
348 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_HexagonVector()
371 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_HexagonVector()
416 LocVT == MVT::v32i32 || LocVT == MVT::v16i64 || in RetCC_Hexagon()
418 LocVT = MVT::v32i32; in RetCC_Hexagon()
419 ValVT = MVT::v32i32; in RetCC_Hexagon()
436 if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) { in RetCC_Hexagon()
488 } else if (LocVT == MVT::v32i32) { in RetCC_HexagonVector()
546 ty == MVT::v16i64 || ty == MVT::v32i32 || ty == MVT::v64i16 || in IsHvxVectorType()
885 (UseHVX && UseHVXDbl) && (VT == MVT::v32i32 || VT == MVT::v16i64 || in getIndexedAddressParts()
[all …]
DHexagonRegisterInfo.td221 [v128i8, v64i16, v32i32, v16i64], 1024,
225 [v128i8, v64i16, v32i32, v16i64], 1024,
DHexagonInstrInfoV60.td782 defm : STrivv_pats <v32i32, v64i32>;
816 defm : vS32b_ai_pats <v16i32, v32i32>;
841 defm : LDrivv_pats <v32i32, v64i32>;
869 defm : vL32b_ai_pats <v16i32, v32i32>;
1543 def: Pat<(v32i32 (HexagonVCOMBINE (v16i32 VectorRegs:$Vs),
1547 def: Pat<(v64i32 (HexagonVCOMBINE (v32i32 VecDblRegs:$Vs),
1548 (v32i32 VecDblRegs:$Vt))),
DHexagonISelDAGToDAG.cpp414 } else if (LoadedVT == MVT::v32i32 || LoadedVT == MVT::v16i64 || in SelectIndexedLoad()
531 else if (StoredVT == MVT::v32i32 || StoredVT == MVT::v16i64 || in SelectIndexedStore()
572 else if (StoredVT == MVT::v32i32 || StoredVT == MVT::v16i64 || in SelectIndexedStore()
DHexagonInstrInfoVector.td83 defm : bitconvert_dblvec<v32i32, v128i8>;
DHexagonInstrInfo.cpp2291 if (VT == MVT::v32i32 || VT == MVT::v16i64 || in isValidAutoIncImm()
/external/llvm/lib/IR/
DValueTypes.cpp170 case MVT::v32i32: return "v32i32"; in getEVTString()
248 case MVT::v32i32: return VectorType::get(Type::getInt32Ty(Context), 32); in getTypeForEVT()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp103 case MVT::v32i32: return "MVT::v32i32"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td191 def llvm_v32i32_ty : LLVMType<v32i32>; // 32 x i32