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Searched refs:vreg (Results 1 – 25 of 59) sorted by relevance

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/external/v8/test/unittests/compiler/
Dinstruction-sequence-unittest.h51 TestOperand(TestOperandType type, VReg vreg, int value = kNoValue)
52 : type_(type), vreg_(vreg), value_(value) {} in type_()
66 static TestOperand Reg(VReg vreg, int index = kNoValue) {
69 return TestOperand(type, vreg, index);
74 static TestOperand Slot(VReg vreg, int index = kNoValue) {
77 return TestOperand(type, vreg, index);
87 static TestOperand Use(VReg vreg) { return TestOperand(kNone, vreg); } in Use() argument
91 static TestOperand Unique(VReg vreg) { return TestOperand(kUnique, vreg); } in Unique() argument
93 static TestOperand UniqueReg(VReg vreg) { in UniqueReg() argument
94 return TestOperand(kUniqueRegister, vreg); in UniqueReg()
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Dinstruction-sequence-unittest.cc150 VReg vreg = NewReg(); in Define() local
151 InstructionOperand outputs[1]{ConvertOutputOp(vreg, output_op)}; in Define()
153 return vreg; in Define()
194 VReg vreg) { in SetInput() argument
195 CHECK(vreg.value_ != kNoValue); in SetInput()
196 phi->SetInput(input, vreg.value_); in SetInput()
202 VReg vreg = NewReg(); in DefineConstant() local
203 sequence()->AddConstant(vreg.value_, Constant(imm)); in DefineConstant()
204 InstructionOperand outputs[1]{ConstantOperand(vreg.value_)}; in DefineConstant()
206 return vreg; in DefineConstant()
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Dlive-range-unittest.cc435 TopLevelLiveRange* vreg = TestRangeBuilder(zone()).Id(2).Build(0, 100); in TEST_F() local
436 EXPECT_EQ(2, vreg->vreg()); in TEST_F()
437 EXPECT_EQ(0, vreg->relative_id()); in TEST_F()
441 vreg->SetSplinter(splinter); in TEST_F()
442 vreg->Splinter(LifetimePosition::FromInt(4), LifetimePosition::FromInt(12), in TEST_F()
445 EXPECT_EQ(101, splinter->vreg()); in TEST_F()
448 LiveRange* child = vreg->SplitAt(LifetimePosition::FromInt(50), zone()); in TEST_F()
458 vreg->Merge(splinter, zone()); in TEST_F()
/external/valgrind/VEX/priv/
Dhost_generic_reg_alloc2.c119 HReg vreg; member
181 if (HRegUsage__contains(&reg_usages_in[m], state[k].vreg)) in findMostDistantlyMentionedVReg()
195 static void sanity_check_spill_offset ( VRegLR* vreg ) in sanity_check_spill_offset() argument
197 switch (vreg->reg_class) { in sanity_check_spill_offset()
199 vassert(0 == ((UShort)vreg->spill_offset % 16)); break; in sanity_check_spill_offset()
201 vassert(0 == ((UShort)vreg->spill_offset % 8)); break; in sanity_check_spill_offset()
483 (*ppReg)(rreg_state[z].vreg); \ in doRegisterAllocation()
523 rreg_state[j].vreg = INVALID_HREG; in doRegisterAllocation()
604 HReg vreg = reg_usage_arr[ii].vRegs[j]; in doRegisterAllocation() local
605 vassert(hregIsVirtual(vreg)); in doRegisterAllocation()
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/external/v8/src/compiler/
Dlive-range-separator.cc50 DCHECK_NULL(data->live_ranges()[splinter->vreg()]); in CreateSplinter()
51 data->live_ranges()[splinter->vreg()] = splinter; in CreateSplinter()
55 TRACE("creating splinter for range %d between %d and %d\n", range->vreg(), in CreateSplinter()
108 for (size_t vreg = 0; vreg < virt_reg_count; ++vreg) { in Splinter() local
109 TopLevelLiveRange *range = data()->live_ranges()[vreg]; in Splinter()
155 int to_remove = range->vreg(); in Merge()
Dregister-allocator-verifier.cc160 int vreg = unallocated->virtual_register(); in BuildConstraint() local
161 constraint->virtual_register_ = vreg; in BuildConstraint()
163 constraint->type_ = sequence()->IsFP(vreg) ? kFPSlot : kSlot; in BuildConstraint()
169 if (sequence()->IsFP(vreg)) { in BuildConstraint()
189 if (sequence()->IsFP(vreg)) { in BuildConstraint()
196 constraint->type_ = sequence()->IsFP(vreg) ? kFPSlot : kSlot; in BuildConstraint()
534 int vreg = pair.second; in VerifyGapMoves() local
541 vreg); in VerifyGapMoves()
547 pending, vreg); in VerifyGapMoves()
549 new (zone()) FinalAssessment(vreg, pending); in VerifyGapMoves()
Dregister-allocator.cc839 TopLevelLiveRange::TopLevelLiveRange(int vreg, MachineRepresentation rep) in TopLevelLiveRange() argument
841 vreg_(vreg), in TopLevelLiveRange()
857 return IsSplinter() ? splintered_from()->vreg() : vreg(); in debug_virt_reg()
1093 TRACE("Shorten live range %d to [%d\n", vreg(), start.value()); in ShortenTo()
1103 TRACE("Ensure live range %d in interval [%d %d[\n", vreg(), start.value(), in EnsureInterval()
1124 TRACE("Add to live range %d interval [%d %d[\n", vreg(), start.value(), in AddUseInterval()
1151 TRACE("Add to live range %d use position %d\n", vreg(), pos.value()); in AddUsePosition()
1197 os << "Range: " << range->TopLevel()->vreg() << ":" << range->relative_id() in operator <<()
1324 os << range->vreg() << " "; in Print()
1429 int vreg = virtual_register_count_++; in GetNextLiveRangeId() local
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Dgraph-visualizer.cc258 void PrintLiveRange(const LiveRange* range, const char* type, int vreg);
547 int vreg = range->vreg(); in PrintLiveRangeChain() local
550 PrintLiveRange(child, type, vreg); in PrintLiveRangeChain()
555 int vreg) { in PrintLiveRange() argument
558 os_ << vreg << ":" << range->relative_id() << " " << type; in PrintLiveRange()
592 os_ << " " << vreg; in PrintLiveRange()
Dregister-allocator-verifier.h213 void AddDelayedAssessment(InstructionOperand op, int vreg) { in AddDelayedAssessment() argument
216 map_.insert(std::make_pair(op, vreg)); in AddDelayedAssessment()
218 CHECK_EQ(it->second, vreg); in AddDelayedAssessment()
/external/vixl/src/vixl/a64/
Dsimulator-a64.cc652 (lane_size_in_bytes == kSRegSizeInBytes) ? vreg(code).Get<float>(lane) in PrintVRegisterFPHelper()
653 : vreg(code).Get<double>(lane); in PrintVRegisterFPHelper()
1996 LogicVRegister(vreg(dst)).SetUint(kFormatD, 1, xreg(src)); in VisitFPIntegerConvert()
1999 set_xreg(dst, LogicVRegister(vreg(src)).Uint(kFormatD, 1)); in VisitFPIntegerConvert()
2164 SimVRegister& rd = vreg(instr->Rd()); in VisitFPDataProcessing1Source()
2165 SimVRegister& rn = vreg(instr->Rn()); in VisitFPDataProcessing1Source()
2174 case FABS_s: fabs_(kFormatS, vreg(fd), vreg(fn)); return; in VisitFPDataProcessing1Source()
2175 case FABS_d: fabs_(kFormatD, vreg(fd), vreg(fn)); return; in VisitFPDataProcessing1Source()
2176 case FNEG_s: fneg(kFormatS, vreg(fd), vreg(fn)); return; in VisitFPDataProcessing1Source()
2177 case FNEG_d: fneg(kFormatD, vreg(fd), vreg(fn)); return; in VisitFPDataProcessing1Source()
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/external/v8/test/cctest/compiler/
Dtest-instruction.cc84 UnallocatedOperand Unallocated(int vreg) { in Unallocated() argument
85 return UnallocatedOperand(UnallocatedOperand::ANY, vreg); in Unallocated()
281 int vreg = 15; in TEST() local
283 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg), in TEST()
284 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg), in TEST()
285 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg), in TEST()
286 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg)}; in TEST()
289 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg), in TEST()
290 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg), in TEST()
291 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg), in TEST()
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/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_wm_debug.c45 else if( value - c->vreg >= 0 && in brw_wm_print_value()
46 value - c->vreg < BRW_WM_MAX_VREG) in brw_wm_print_value()
47 printf("r%ld", (long) (value - c->vreg)); in brw_wm_print_value()
Dbrw_wm.c285 void *vreg = c->vreg; in do_wm_prog() local
290 c->vreg = vreg; in do_wm_prog()
311 c->vreg = rzalloc_array(c, struct brw_wm_value, BRW_WM_MAX_VREG); in do_wm_prog()
Dbrw_wm_pass0.c52 memset(&c->vreg[c->nr_vreg], 0, sizeof(*c->vreg)); in get_value()
53 return &c->vreg[c->nr_vreg++]; in get_value()
/external/llvm/test/CodeGen/PowerPC/
Dquadint-return.ll17 ; CHECK: %X3<def> = COPY %vreg
18 ; CHECK-NEXT: %X4<def> = COPY %vreg
/external/v8/src/x64/
Dassembler-x64-inl.h222 void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg, in emit_vex_prefix() argument
228 emit_vex3_byte2(w, vreg, l, pp); in emit_vex_prefix()
231 emit_vex2_byte1(reg, vreg, l, pp); in emit_vex_prefix()
236 void Assembler::emit_vex_prefix(Register reg, Register vreg, Register rm, in emit_vex_prefix() argument
240 XMMRegister ivreg = {vreg.code()}; in emit_vex_prefix()
246 void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg, in emit_vex_prefix() argument
252 emit_vex3_byte2(w, vreg, l, pp); in emit_vex_prefix()
255 emit_vex2_byte1(reg, vreg, l, pp); in emit_vex_prefix()
260 void Assembler::emit_vex_prefix(Register reg, Register vreg, const Operand& rm, in emit_vex_prefix() argument
264 XMMRegister ivreg = {vreg.code()}; in emit_vex_prefix()
Dassembler-x64.cc3973 void Assembler::bmi1q(byte op, Register reg, Register vreg, Register rm) { in bmi1q() argument
3976 emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW1); in bmi1q()
3982 void Assembler::bmi1q(byte op, Register reg, Register vreg, const Operand& rm) { in bmi1q() argument
3985 emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW1); in bmi1q()
3991 void Assembler::bmi1l(byte op, Register reg, Register vreg, Register rm) { in bmi1l() argument
3994 emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW0); in bmi1l()
4000 void Assembler::bmi1l(byte op, Register reg, Register vreg, const Operand& rm) { in bmi1l() argument
4003 emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW0); in bmi1l()
4141 void Assembler::bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg, in bmi2q() argument
4145 emit_vex_prefix(reg, vreg, rm, kLZ, pp, k0F38, kW1); in bmi2q()
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/external/llvm/test/CodeGen/AArch64/
Dtailcall_misched_graph.ll29 ; CHECK: [[VRA:%vreg.*]]<def> = LDRXui <fi#-1>
30 ; CHECK: [[VRB:%vreg.*]]<def> = LDRXui <fi#-2>
31 ; CHECK: STRXui %vreg{{.*}}, <fi#-4>
Darm64-fast-isel-rem.ll7 ; CHECK-SSA: [[QUOTREG:%vreg[0-9]+]]<def> = SDIVWr
9 ; CHECK-SSA: {{%vreg[0-9]+}}<def> = MSUBWrrr [[QUOTREG]]
/external/llvm/test/CodeGen/ARM/
Dmisched-copy-arm.ll36 ; CHECK: %[[R4:vreg[0-9]+]]<def>, %[[R1:vreg[0-9]+]]<def,tied2> = t2LDR_PRE %[[R1]]<tied1>
37 ; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R1]]
38 ; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R4]]
Dfast-isel-shift-materialize.ll6 ; When materializing the '2' for the shifts below, the second shift kills the vreg
7 ; we materialize in to. However, the first shift was also killing that vreg.
Dfast-isel-remat-same-constant.ll7 ; generated by the GEPs. The first add generated killed the vreg for the #6680 constant which shou…
9 ; down. This meant the next use of the vreg for #6680 was after the first which had killed it.
Dfast-isel-update-valuemap-for-extract.ll6 ; This test ensures that when fast-isel rewrites uses of the vreg for %tmp29, it also
/external/vixl/test/
Dtest-utils-a64.cc145 const VRegister& vreg) { in Equal128() argument
146 VIXL_ASSERT(vreg.Is128Bits()); in Equal128()
148 vec128_t result = core->qreg(vreg.code()); in Equal128()
/external/llvm/test/CodeGen/X86/
Dearly-ifcvt-crash.ll11 ; on an inline asm instruction is not a vreg def.

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