/external/llvm/lib/Target/X86/ |
D | X86TargetTransformInfo.cpp | 561 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost() 564 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, in getCastInstrCost() 566 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, in getCastInstrCost() 568 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, in getCastInstrCost() 571 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, in getCastInstrCost() 611 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, in getCastInstrCost() 613 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, in getCastInstrCost() 615 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost() 617 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, in getCastInstrCost() 619 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, in getCastInstrCost() [all …]
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D | X86ISelLowering.cpp | 748 setOperationAction(ISD::SIGN_EXTEND, VT, Expand); in X86TargetLowering() 1136 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom); in X86TargetLowering() 1137 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom); in X86TargetLowering() 1138 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom); in X86TargetLowering() 1448 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom); in X86TargetLowering() 1449 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom); in X86TargetLowering() 1450 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom); in X86TargetLowering() 1451 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom); in X86TargetLowering() 1452 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom); in X86TargetLowering() 1454 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom); in X86TargetLowering() [all …]
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D | X86FastISel.cpp | 1083 ISD::SIGN_EXTEND; in X86SelectRet() 2310 InputReg = fastEmit_r(MVT::i16, MVT::i32, ISD::SIGN_EXTEND, InputReg, in fastLowerIntrinsicCall() 2965 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall() 2989 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64TargetTransformInfo.cpp | 197 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost() 199 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost() 201 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost() 203 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, in getCastInstrCost() 205 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost() 207 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost() 209 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, in getCastInstrCost() 211 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
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/external/llvm/lib/Target/ARM/ |
D | ARMTargetTransformInfo.cpp | 79 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost() 81 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost() 87 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost() 89 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost() 91 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost() 93 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost() 95 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost() 224 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 }, in getCastInstrCost()
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-AnInfiniteLoopInDAGCombine.ll | 10 ; As we think the (2) optimization from SIGN_EXTEND to ANY_EXTEND is
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D | rm_redundant_cmp.ll | 246 ; The optimization of ZERO_EXTEND and SIGN_EXTEND in type legalization stage can't assert
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/external/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 389 SIGN_EXTEND, enumerator
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | DAGCombiner.cpp | 990 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteOperand() 1401 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); in visit() 1489 case ISD::SIGN_EXTEND: in combine() 1769 if (N0.getOpcode() == ISD::SIGN_EXTEND && in visitADD() 1771 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { in visitADD() 2502 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); in visitMULHS() 2503 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); in visitMULHS() 2616 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); in visitSMUL_LOHI() 2617 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); in visitSMUL_LOHI() 2729 N0.getOpcode() == ISD::SIGN_EXTEND || in SimplifyBinOpWithSameOpcodeHands() [all …]
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D | FunctionLoweringInfo.cpp | 78 ExtendKind = ISD::SIGN_EXTEND; in getPreferredExtendForValue()
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D | LegalizeVectorOps.cpp | 297 case ISD::SIGN_EXTEND: in LegalizeOp() 453 ISD::SIGN_EXTEND; in PromoteINT_TO_FP()
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D | LegalizeVectorTypes.cpp | 96 case ISD::SIGN_EXTEND: in ScalarizeVectorResult() 438 case ISD::SIGN_EXTEND: in ScalarizeVectorOperand() 659 case ISD::SIGN_EXTEND: in SplitVectorResult() 1445 case ISD::SIGN_EXTEND: in SplitVectorOperand() 2077 case ISD::SIGN_EXTEND: in WidenVectorResult() 2973 case ISD::SIGN_EXTEND: in WidenVectorOperand() 3060 case ISD::SIGN_EXTEND: in WidenVecOp_EXTEND()
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D | LegalizeFloatTypes.cpp | 710 SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, in SoftenFloatRes_XINT_TO_FP() 1401 Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, in ExpandFloatRes_XINT_TO_FP() 1409 Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, in ExpandFloatRes_XINT_TO_FP() 1413 Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src); in ExpandFloatRes_XINT_TO_FP()
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D | SelectionDAGDumper.cpp | 240 case ISD::SIGN_EXTEND: return "sign_extend"; in getOperationName()
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D | LegalizeIntegerTypes.cpp | 105 case ISD::SIGN_EXTEND: in PromoteIntegerResult() 348 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteIntRes_Constant() 455 if (N->getOpcode() == ISD::SIGN_EXTEND) in PromoteIntRes_INT_EXTEND() 895 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; in PromoteIntegerOperand() 1323 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; in ExpandIntegerResult() 2338 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0)); in ExpandIntRes_SIGN_EXTEND()
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D | SelectionDAG.cpp | 235 return ISD::SIGN_EXTEND; in getExtForLoadExtType() 1019 getNode(ISD::SIGN_EXTEND, DL, VT, Op) : in getSExtOrTrunc() 2304 case ISD::SIGN_EXTEND: { in computeKnownBits() 2547 case ISD::SIGN_EXTEND: in ComputeNumSignBits() 2874 case ISD::SIGN_EXTEND: in getNode() 3032 case ISD::SIGN_EXTEND: in getNode() 3042 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) in getNode() 3076 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || in getNode() 3102 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || in getNode() 3386 ScalarResult = getNode(ISD::SIGN_EXTEND, DL, LegalSVT, ScalarResult); in FoldConstantVectorArithmetic()
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/external/mesa3d/src/gallium/drivers/radeon/ |
D | AMDILISelLowering.cpp | 183 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Expand); in InitAMDILLowering() 198 setOperationAction(ISD::SIGN_EXTEND, MVT::v2f64, Expand); in InitAMDILLowering()
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D | SIISelLowering.cpp | 424 && Arg0.getOpcode() == ISD::SIGN_EXTEND in PerformDAGCombine()
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/external/llvm/lib/Target/MSP430/ |
D | MSP430ISelLowering.cpp | 114 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom); in MSP430TargetLowering() 195 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); in LowerOperation() 611 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZISelDAGToDAG.cpp | 532 if (IndexOpcode == ISD::SIGN_EXTEND || in shouldUseLA() 822 case ISD::SIGN_EXTEND: { in expandRxSBG()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonISelDAGToDAG.cpp | 629 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) { in SelectMul() 655 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) { in SelectMul() 1503 case ISD::SIGN_EXTEND: in isValueExtension()
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D | HexagonISelLowering.cpp | 736 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall() 1229 unsigned ExtOpc = ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND in LowerSETCC() 1249 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS); in LowerSETCC() 1250 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS); in LowerSETCC() 1255 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS); in LowerSETCC() 1256 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS); in LowerSETCC()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCISelLowering.cpp | 855 setTargetDAGCombine(ISD::SIGN_EXTEND); in PPCTargetLowering() 4955 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4() 5526 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_Darwin() 5808 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerReturn() 6457 SINT.getOpcode() == ISD::SIGN_EXTEND) || in LowerINT_TO_FP() 6551 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64, in LowerINT_TO_FP() 9512 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND && in DAGCombineTruncBoolExt() 9524 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND && in DAGCombineTruncBoolExt() 9534 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND || in DAGCombineTruncBoolExt() 9565 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND || in DAGCombineTruncBoolExt() [all …]
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/external/llvm/lib/Target/BPF/ |
D | BPFISelLowering.cpp | 321 Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
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/external/llvm/lib/CodeGen/ |
D | TargetLoweringBase.cpp | 1467 ExtendKind = ISD::SIGN_EXTEND; in GetReturnInfo() 1581 case SExt: return ISD::SIGN_EXTEND; in InstructionOpcodeToISD()
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