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Searched refs:AT (Results 1 – 25 of 25) sorted by relevance

/art/runtime/interpreter/mterp/mips64/
Dheader.S170 sll AT, \reg, 7
171 daddu AT, rIBASE, AT
172 jic AT, 0
185 dlsa AT, \vreg, rFP, 2
186 lw \reg, 0(AT)
191 dlsa AT, \vreg, rFP, 2
192 lwu \reg, 0(AT)
197 dlsa AT, \vreg, rFP, 2
198 lwc1 \reg, 0(AT)
203 dlsa AT, \vreg, rFP, 2
[all …]
/art/runtime/interpreter/mterp/mips/
Dheader.S81 #define AT $$at /* assembler temp */ macro
200 sll AT, rs, sa; \
201 addu rd, AT, rt; \
326 EAS2(AT, rFP, rix); \
327 l.s rd, (AT); \
339 sll AT, rix, 2; \
340 addu t8, rFP, AT; \
342 addu t8, rREFS, AT; \
356 sll AT, rix, 2; \
357 addu t8, rFP, AT; \
[all …]
/art/compiler/optimizing/
Dintrinsics_mips.cc286 __ LoadConst32(AT, 0x00FF00FF); in GenReverse()
287 __ And(TMP, out, AT); in GenReverse()
290 __ And(out, out, AT); in GenReverse()
297 __ LoadConst32(AT, 0x0F0F0F0F); in GenReverse()
298 __ And(TMP, out, AT); in GenReverse()
301 __ And(out, out, AT); in GenReverse()
303 __ LoadConst32(AT, 0x33333333); in GenReverse()
304 __ And(TMP, out, AT); in GenReverse()
307 __ And(out, out, AT); in GenReverse()
309 __ LoadConst32(AT, 0x55555555); in GenReverse()
[all …]
Dintrinsics_mips64.cc422 __ LoadConst32(AT, 0x55555555); in GenBitCount()
423 __ And(TMP, TMP, AT); in GenBitCount()
425 __ LoadConst32(AT, 0x33333333); in GenBitCount()
426 __ And(out, TMP, AT); in GenBitCount()
428 __ And(TMP, TMP, AT); in GenBitCount()
432 __ LoadConst32(AT, 0x0F0F0F0F); in GenBitCount()
433 __ And(out, out, AT); in GenBitCount()
439 __ LoadConst64(AT, 0x5555555555555555L); in GenBitCount()
440 __ And(TMP, TMP, AT); in GenBitCount()
442 __ LoadConst64(AT, 0x3333333333333333L); in GenBitCount()
[all …]
Dcode_generator_mips.cc727 DCHECK_NE(temp1_, AT); in EmitNativeCode()
785 Register tmp = AT; // Value in memory. in EmitNativeCode()
1231 __ MoveFromFpuHigh(AT, f1); in EmitSwap()
1235 __ Move(r2_h, AT); in EmitSwap()
1836 Register card = AT; in MarkGCCard()
1864 blocked_core_registers_[AT] = true; in SetupBlockedRegisters()
1967 __ LoadConst32(AT, mirror::Class::kStatusInitialized); in GenerateClassInitializationCheck()
1968 __ Blt(TMP, AT, slow_path->GetEntryLabel()); in GenerateClassInitializationCheck()
2217 __ Sltiu(AT, dst_low, low); in HandleBinaryOp()
2222 __ Sltu(AT, dst_low, TMP); in HandleBinaryOp()
[all …]
Dcode_generator_mips64.cc676 DCHECK_NE(temp1_, AT); in EmitNativeCode()
730 GpuRegister tmp = AT; // Value in memory. in EmitNativeCode()
1299 GpuRegister gpr = AT; in MoveLocation()
1518 GpuRegister card = AT; in MarkGCCard()
1716 blocked_core_registers_[AT] = true; in SetupBlockedRegisters()
1799 __ LoadConst32(AT, mirror::Class::kStatusInitialized); in GenerateClassInitializationCheck()
1800 __ Bltc(TMP, AT, slow_path->GetEntryLabel()); in GenerateClassInitializationCheck()
2882 __ Lwu(AT, temp, object_array_data_offset); in VisitCheckCast()
2883 __ MaybeUnpoisonHeapReference(AT); in VisitCheckCast()
2888 __ Bnec(AT, cls, &loop); in VisitCheckCast()
[all …]
Dcode_generator_vector_mips64.cc884 __ Dlsa(AT, index_reg, base, scale); in VecAddress()
886 __ Daddu(AT, base, index_reg); in VecAddress()
888 *adjusted_base = AT; in VecAddress()
Dcode_generator_vector_mips.cc880 __ Lsa(AT, index_reg, base, scale); in VecAddress()
882 __ Addu(AT, base, index_reg); in VecAddress()
884 *adjusted_base = AT; in VecAddress()
/art/compiler/utils/mips/
Dassembler_mips.cc4058 Lui(AT, High16Bits(offset)); in EmitBranch()
4059 Ori(AT, AT, Low16Bits(offset)); in EmitBranch()
4060 Addu(AT, AT, RA); in EmitBranch()
4062 Jr(AT); in EmitBranch()
4078 Lui(AT, High16Bits(offset)); in EmitBranch()
4079 Ori(AT, AT, Low16Bits(offset)); in EmitBranch()
4080 Addu(AT, AT, RA); in EmitBranch()
4082 Jr(AT); in EmitBranch()
4092 Lui(AT, High16Bits(offset)); in EmitBranch()
4093 Ori(AT, AT, Low16Bits(offset)); in EmitBranch()
[all …]
Dassembler_mips32r5_test.cc80 registers_.push_back(new mips::Register(mips::AT)); in SetUpHelpers()
113 secondary_register_names_.emplace(mips::Register(mips::AT), "at"); in SetUpHelpers()
Dassembler_mips.h271 void ShiftAndAdd(Register dst, Register src_idx, Register src_base, int shamt, Register tmp = AT);
623 void Addiu32(Register rt, Register rs, int32_t value, Register rtmp = AT);
675 CHECK_NE(temp, AT); // Must not use AT as temp, so as not to overwrite the adjusted base.
686 temp = AT;
829 CHECK_NE(reg, AT);
Dassembler_mips_test.cc58 registers_.push_back(new mips::Register(mips::AT)); in SetUpHelpers()
91 secondary_register_names_.emplace(mips::Register(mips::AT), "at"); in SetUpHelpers()
2501 __ Xor(mips::AT, mips::T0, mips::T1); in TEST_F()
2504 __ Subu(mips::T0, mips::T1, mips::AT); in TEST_F()
Dassembler_mips32r6_test.cc93 registers_.push_back(new mips::Register(mips::AT)); in SetUpHelpers()
126 secondary_register_names_.emplace(mips::Register(mips::AT), "at"); in SetUpHelpers()
/art/runtime/arch/mips/
Dregisters_mips.h31 AT = 1, // Assembler temporary. enumerator
Dquick_method_frame_info_mips.h41 (1 << art::mips::AT) | (1 << art::mips::V0) | (1 << art::mips::V1) |
/art/runtime/arch/mips64/
Dregisters_mips64.h31 AT = 1, // Assembler temporary. enumerator
Dquick_method_frame_info_mips64.h43 (1 << art::mips64::AT) | (1 << art::mips64::V0) | (1 << art::mips64::V1) |
/art/compiler/utils/mips64/
Dassembler_mips64.cc2739 Auipc(AT, High16Bits(offset)); in EmitBranch()
2740 Jic(AT, Low16Bits(offset)); in EmitBranch()
2746 Auipc(AT, High16Bits(offset)); in EmitBranch()
2747 Jic(AT, Low16Bits(offset)); in EmitBranch()
2752 Auipc(AT, High16Bits(offset)); in EmitBranch()
2753 Jialc(AT, Low16Bits(offset)); in EmitBranch()
2760 Auipc(AT, High16Bits(offset)); in EmitBranch()
2761 Daddiu(lhs, AT, Low16Bits(offset)); in EmitBranch()
2767 Auipc(AT, High16Bits(offset)); in EmitBranch()
2768 Lw(lhs, AT, Low16Bits(offset)); in EmitBranch()
[all …]
Dmanaged_register_mips64_test.cc38 reg = Mips64ManagedRegister::FromGpuRegister(AT); in TEST()
43 EXPECT_EQ(AT, reg.AsGpuRegister()); in TEST()
Dassembler_mips64.h810 void Daddiu64(GpuRegister rt, GpuRegister rs, int64_t value, GpuRegister rtmp = AT); // MIPS64
952 CHECK_NE(temp, AT); // Must not use AT as temp, so as not to overwrite the adjusted base.
961 temp = AT;
1120 CHECK_NE(reg, AT);
Dassembler_mips64_test.cc91 registers_.push_back(new mips64::GpuRegister(mips64::AT)); in SetUpHelpers()
124 secondary_register_names_.emplace(mips64::GpuRegister(mips64::AT), "at"); in SetUpHelpers()
/art/runtime/interpreter/mterp/out/
Dmterp_mips.S88 #define AT $at /* assembler temp */ macro
207 sll AT, rs, sa; \
208 addu rd, AT, rt; \
333 EAS2(AT, rFP, rix); \
334 l.s rd, (AT); \
346 sll AT, rix, 2; \
347 addu t8, rFP, AT; \
349 addu t8, rREFS, AT; \
363 sll AT, rix, 2; \
364 addu t8, rFP, AT; \
[all …]
Dmterp_mips64.S177 sll AT, \reg, 7
178 daddu AT, rIBASE, AT
179 jic AT, 0
192 dlsa AT, \vreg, rFP, 2
193 lw \reg, 0(AT)
198 dlsa AT, \vreg, rFP, 2
199 lwu \reg, 0(AT)
204 dlsa AT, \vreg, rFP, 2
205 lwc1 \reg, 0(AT)
210 dlsa AT, \vreg, rFP, 2
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/art/compiler/jni/quick/mips64/
Dcalling_convention_mips64.cc176 return Mips64ManagedRegister::FromGpuRegister(AT); in ReturnScratchRegister()
/art/compiler/jni/quick/mips/
Dcalling_convention_mips.cc332 return MipsManagedRegister::FromCoreRegister(AT); in ReturnScratchRegister()