Home
last modified time | relevance | path

Searched refs:dst (Results 1 – 25 of 73) sorted by relevance

123

/art/compiler/utils/x86_64/
Dassembler_x86_64.cc106 void X86_64Assembler::movq(CpuRegister dst, const Immediate& imm) { in movq() argument
110 EmitRex64(dst); in movq()
112 EmitRegisterOperand(0, dst.LowBits()); in movq()
115 EmitRex64(dst); in movq()
116 EmitUint8(0xB8 + dst.LowBits()); in movq()
122 void X86_64Assembler::movl(CpuRegister dst, const Immediate& imm) { in movl() argument
125 EmitOptionalRex32(dst); in movl()
126 EmitUint8(0xB8 + dst.LowBits()); in movl()
131 void X86_64Assembler::movq(const Address& dst, const Immediate& imm) { in movq() argument
134 EmitRex64(dst); in movq()
[all …]
Dassembler_x86_64.h355 void movq(CpuRegister dst, const Immediate& src);
356 void movl(CpuRegister dst, const Immediate& src);
357 void movq(CpuRegister dst, CpuRegister src);
358 void movl(CpuRegister dst, CpuRegister src);
360 void movntl(const Address& dst, CpuRegister src);
361 void movntq(const Address& dst, CpuRegister src);
363 void movq(CpuRegister dst, const Address& src);
364 void movl(CpuRegister dst, const Address& src);
365 void movq(const Address& dst, CpuRegister src);
366 void movq(const Address& dst, const Immediate& imm);
[all …]
/art/compiler/utils/x86/
Dassembler_x86.h326 void movl(Register dst, const Immediate& src);
327 void movl(Register dst, Register src);
329 void movl(Register dst, const Address& src);
330 void movl(const Address& dst, Register src);
331 void movl(const Address& dst, const Immediate& imm);
332 void movl(const Address& dst, Label* lbl);
334 void movntl(const Address& dst, Register src);
336 void bswapl(Register dst);
338 void bsfl(Register dst, Register src);
339 void bsfl(Register dst, const Address& src);
[all …]
Dassembler_x86.cc106 void X86Assembler::movl(Register dst, const Immediate& imm) { in movl() argument
108 EmitUint8(0xB8 + dst); in movl()
113 void X86Assembler::movl(Register dst, Register src) { in movl() argument
116 EmitRegisterOperand(src, dst); in movl()
120 void X86Assembler::movl(Register dst, const Address& src) { in movl() argument
123 EmitOperand(dst, src); in movl()
127 void X86Assembler::movl(const Address& dst, Register src) { in movl() argument
130 EmitOperand(src, dst); in movl()
134 void X86Assembler::movl(const Address& dst, const Immediate& imm) { in movl() argument
137 EmitOperand(0, dst); in movl()
[all …]
/art/compiler/optimizing/
Dcode_generator_vector_mips64.cc56 VectorRegister dst = VectorRegisterFrom(locations->Out()); in VisitVecReplicateScalar() local
61 __ FillB(dst, locations->InAt(0).AsRegister<GpuRegister>()); in VisitVecReplicateScalar()
66 __ FillH(dst, locations->InAt(0).AsRegister<GpuRegister>()); in VisitVecReplicateScalar()
70 __ FillW(dst, locations->InAt(0).AsRegister<GpuRegister>()); in VisitVecReplicateScalar()
74 __ FillD(dst, locations->InAt(0).AsRegister<GpuRegister>()); in VisitVecReplicateScalar()
78 __ ReplicateFPToVectorRegister(dst, in VisitVecReplicateScalar()
84 __ ReplicateFPToVectorRegister(dst, in VisitVecReplicateScalar()
146 VectorRegister dst = VectorRegisterFrom(locations->Out()); in VisitVecCnv() local
151 __ Ffint_sW(dst, src); in VisitVecCnv()
165 VectorRegister dst = VectorRegisterFrom(locations->Out()); in VisitVecNeg() local
[all …]
Dcode_generator_vector_mips.cc51 VectorRegister dst = VectorRegisterFrom(locations->Out()); in VisitVecReplicateScalar() local
56 __ FillB(dst, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
61 __ FillH(dst, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
65 __ FillW(dst, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
71 __ ReplicateFPToVectorRegister(dst, FTMP, /* is_double */ true); in VisitVecReplicateScalar()
75 __ ReplicateFPToVectorRegister(dst, in VisitVecReplicateScalar()
81 __ ReplicateFPToVectorRegister(dst, in VisitVecReplicateScalar()
143 VectorRegister dst = VectorRegisterFrom(locations->Out()); in VisitVecCnv() local
148 __ Ffint_sW(dst, src); in VisitVecCnv()
161 VectorRegister dst = VectorRegisterFrom(locations->Out()); in VisitVecNeg() local
[all …]
Dcode_generator_vector_x86.cc145 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecCnv() local
150 __ cvtdq2ps(dst, src); in VisitVecCnv()
163 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecNeg() local
167 __ pxor(dst, dst); in VisitVecNeg()
168 __ psubb(dst, src); in VisitVecNeg()
173 __ pxor(dst, dst); in VisitVecNeg()
174 __ psubw(dst, src); in VisitVecNeg()
178 __ pxor(dst, dst); in VisitVecNeg()
179 __ psubd(dst, src); in VisitVecNeg()
183 __ pxor(dst, dst); in VisitVecNeg()
[all …]
Dcode_generator_vector_x86_64.cc138 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecCnv() local
143 __ cvtdq2ps(dst, src); in VisitVecCnv()
156 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecNeg() local
160 __ pxor(dst, dst); in VisitVecNeg()
161 __ psubb(dst, src); in VisitVecNeg()
166 __ pxor(dst, dst); in VisitVecNeg()
167 __ psubw(dst, src); in VisitVecNeg()
171 __ pxor(dst, dst); in VisitVecNeg()
172 __ psubd(dst, src); in VisitVecNeg()
176 __ pxor(dst, dst); in VisitVecNeg()
[all …]
Dcode_generator_vector_arm64.cc70 VRegister dst = VRegisterFrom(locations->Out()); in VisitVecReplicateScalar() local
76 __ Movi(dst.V16B(), Int64ConstantFrom(src_loc)); in VisitVecReplicateScalar()
78 __ Dup(dst.V16B(), InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
85 __ Movi(dst.V8H(), Int64ConstantFrom(src_loc)); in VisitVecReplicateScalar()
87 __ Dup(dst.V8H(), InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
93 __ Movi(dst.V4S(), Int64ConstantFrom(src_loc)); in VisitVecReplicateScalar()
95 __ Dup(dst.V4S(), InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
101 __ Movi(dst.V2D(), Int64ConstantFrom(src_loc)); in VisitVecReplicateScalar()
103 __ Dup(dst.V2D(), XRegisterFrom(src_loc)); in VisitVecReplicateScalar()
109 __ Fmov(dst.V4S(), src_loc.GetConstant()->AsFloatConstant()->GetValue()); in VisitVecReplicateScalar()
[all …]
Dcode_generator_vector_arm_vixl.cc54 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecReplicateScalar() local
59 __ Vdup(Untyped8, dst, InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
64 __ Vdup(Untyped16, dst, InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
68 __ Vdup(Untyped32, dst, InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
130 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecNeg() local
134 __ Vneg(DataTypeValue::S8, dst, src); in VisitVecNeg()
139 __ Vneg(DataTypeValue::S16, dst, src); in VisitVecNeg()
143 __ Vneg(DataTypeValue::S32, dst, src); in VisitVecNeg()
158 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecAbs() local
162 __ Vabs(DataTypeValue::S8, dst, src); in VisitVecAbs()
[all …]
Dcode_generator_mips.cc1500 FRegister dst = destination.AsFpuRegister<FRegister>(); in MoveLocation() local
1503 __ Mtc1(src_low, dst); in MoveLocation()
1504 __ MoveToFpuHigh(src_high, dst); in MoveLocation()
1569 Register dst = destination.AsRegister<Register>(); in MoveConstant() local
1570 __ LoadConst32(dst, value); in MoveConstant()
1615 Register dst = destination.AsRegister<Register>(); in MoveConstant() local
1616 __ LoadConst32(dst, value); in MoveConstant()
2058 Register dst = locations->Out().AsRegister<Register>(); in HandleBinaryOp() local
2073 __ Andi(dst, lhs, rhs_imm); in HandleBinaryOp()
2075 __ And(dst, lhs, rhs_reg); in HandleBinaryOp()
[all …]
Dcode_generator_mips64.cc1884 GpuRegister dst = locations->Out().AsRegister<GpuRegister>(); in HandleBinaryOp() local
1899 __ Andi(dst, lhs, rhs_imm); in HandleBinaryOp()
1901 __ And(dst, lhs, rhs_reg); in HandleBinaryOp()
1904 __ Ori(dst, lhs, rhs_imm); in HandleBinaryOp()
1906 __ Or(dst, lhs, rhs_reg); in HandleBinaryOp()
1909 __ Xori(dst, lhs, rhs_imm); in HandleBinaryOp()
1911 __ Xor(dst, lhs, rhs_reg); in HandleBinaryOp()
1915 __ Addiu(dst, lhs, rhs_imm); in HandleBinaryOp()
1917 __ Addu(dst, lhs, rhs_reg); in HandleBinaryOp()
1920 __ Daddiu(dst, lhs, rhs_imm); in HandleBinaryOp()
[all …]
/art/runtime/
Dreflection-inl.h36 JValue* dst) { in ConvertPrimitiveValueNoThrow() argument
39 dst->SetJ(src.GetJ()); in ConvertPrimitiveValueNoThrow()
50 dst->SetS(src.GetI()); in ConvertPrimitiveValueNoThrow()
57 dst->SetI(src.GetI()); in ConvertPrimitiveValueNoThrow()
64 dst->SetJ(src.GetI()); in ConvertPrimitiveValueNoThrow()
71 dst->SetF(src.GetI()); in ConvertPrimitiveValueNoThrow()
74 dst->SetF(src.GetJ()); in ConvertPrimitiveValueNoThrow()
81 dst->SetD(src.GetI()); in ConvertPrimitiveValueNoThrow()
84 dst->SetD(src.GetJ()); in ConvertPrimitiveValueNoThrow()
87 dst->SetD(src.GetF()); in ConvertPrimitiveValueNoThrow()
[all …]
/art/runtime/jdwp/
Djdwp_bits.h109 static inline void Write1BE(uint8_t** dst, uint8_t value) { in Write1BE() argument
110 Set1(*dst, value); in Write1BE()
111 *dst += sizeof(value); in Write1BE()
114 static inline void Write2BE(uint8_t** dst, uint16_t value) { in Write2BE() argument
115 Set2BE(*dst, value); in Write2BE()
116 *dst += sizeof(value); in Write2BE()
119 static inline void Write4BE(uint8_t** dst, uint32_t value) { in Write4BE() argument
120 Set4BE(*dst, value); in Write4BE()
121 *dst += sizeof(value); in Write4BE()
124 static inline void Write8BE(uint8_t** dst, uint64_t value) { in Write8BE() argument
[all …]
/art/runtime/interpreter/mterp/mips/
Dheader.S440 #define SET_VREG_GOTO(rd, rix, dst) \ argument
442 GET_OPCODE_TARGET(dst); \
446 jalr zero, dst; \
450 #define SET_VREG_GOTO(rd, rix, dst) \ argument
452 GET_OPCODE_TARGET(dst); \
459 jalr zero, dst; \
466 #define SET_VREG_OBJECT_GOTO(rd, rix, dst) \ argument
468 GET_OPCODE_TARGET(dst); \
472 jalr zero, dst; \
476 #define SET_VREG_OBJECT_GOTO(rd, rix, dst) \ argument
[all …]
/art/test/201-built-in-except-detail-messages/src/
DMain.java136 Integer[] dst = new Integer[10]; in arrayStore() local
137 System.arraycopy(src, 1, dst, 0, 5); in arrayStore()
145 int[] dst = new int[1]; in arrayStore() local
146 System.arraycopy(src, 0, dst, 0, 1); in arrayStore()
153 Runnable[] dst = new Runnable[1]; in arrayStore() local
154 System.arraycopy(src, 0, dst, 0, 1); in arrayStore()
161 double[][] dst = new double[1][]; in arrayStore() local
162 System.arraycopy(src, 0, dst, 0, 1); in arrayStore()
169 Object[] dst = new Object[1]; in arrayStore() local
170 System.arraycopy(src, 0, dst, 0, 1); in arrayStore()
[all …]
/art/test/020-string/src/
DMain.java131 char[] dst = new char[7]; in copyTest() local
142 src.getChars(-1, 9, dst, 0); in copyTest()
149 src.getChars(2, 19, dst, 0); in copyTest()
156 src.getChars(2, 1, dst, 0); in copyTest()
163 src.getChars(2, 10, dst, 0); in copyTest()
169 src.getChars(2, 9, dst, 0); in copyTest()
170 System.out.println(new String(dst)); in copyTest()
/art/compiler/utils/arm/
Djni_macro_assembler_arm_vixl.cc244 ArmManagedRegister dst = dest.AsArm(); in LoadRef() local
245 CHECK(dst.IsCoreRegister() && dst.IsCoreRegister()) << dst; in LoadRef()
247 temps.Exclude(dst.AsVIXLRegister(), base.AsArm().AsVIXLRegister()); in LoadRef()
249 dst.AsVIXLRegister(), in LoadRef()
254 asm_.MaybeUnpoisonHeapReference(dst.AsVIXLRegister()); in LoadRef()
291 ArmManagedRegister dst = m_dst.AsArm(); in LoadRawPtrFromThread() local
292 CHECK(dst.IsCoreRegister()) << dst; in LoadRawPtrFromThread()
294 temps.Exclude(dst.AsVIXLRegister()); in LoadRawPtrFromThread()
295 asm_.LoadFromOffset(kLoadWord, dst.AsVIXLRegister(), tr, offs.Int32Value()); in LoadRawPtrFromThread()
343 ArmManagedRegister dst = m_dst.AsArm(); in Move() local
[all …]
/art/runtime/base/
Dstrlcpy.h31 static inline size_t strlcpy(char* dst, const char* src, size_t size) { in strlcpy() argument
33 return snprintf(dst, size, "%s", src); in strlcpy()
Dsafe_copy.cc31 ssize_t SafeCopy(void *dst, const void *src, size_t len) { in SafeCopy() argument
34 .iov_base = dst, in SafeCopy()
76 UNUSED(dst, src, len); in SafeCopy()
Dsafe_copy_test.cc94 char* dst = static_cast<char*>(dst_map); in TEST() local
95 ASSERT_EQ(0, mprotect(dst + 3 * kPageSize, kPageSize, PROT_NONE)); in TEST()
101 SafeCopy(dst + 1024, src + 512, kPageSize * 3 - 1024)); in TEST()
102 EXPECT_EQ(0, memcmp(dst + 1024, src + 512, kPageSize * 3 - 1024)); in TEST()
/art/test/646-checker-arraycopy-large-cst-pos/src/
DMain.java30 Object[] dst = new Object[2048]; in test() local
34 System.arraycopy(src, 0, dst, 1024, 64); in test()
/art/runtime/base/unix_file/
Drandom_access_file_utils.cc23 bool CopyFile(const RandomAccessFile& src, RandomAccessFile* dst) { in CopyFile() argument
30 if (dst->Write(&buf[0], n, offset) != n) { in CopyFile()
/art/compiler/utils/arm64/
Djni_macro_assembler_arm64.cc293 Arm64ManagedRegister dst = m_dst.AsArm64(); in LoadRef() local
294 CHECK(dst.IsXRegister()) << dst; in LoadRef()
295 LoadWFromOffset(kLoadWord, dst.AsOverlappingWRegister(), SP, offs.Int32Value()); in LoadRef()
302 Arm64ManagedRegister dst = m_dst.AsArm64(); in LoadRef() local
304 CHECK(dst.IsXRegister() && base.IsXRegister()); in LoadRef()
305 LoadWFromOffset(kLoadWord, dst.AsOverlappingWRegister(), base.AsXRegister(), in LoadRef()
308 WRegister ref_reg = dst.AsOverlappingWRegister(); in LoadRef()
316 Arm64ManagedRegister dst = m_dst.AsArm64(); in LoadRawPtr() local
318 CHECK(dst.IsXRegister() && base.IsXRegister()); in LoadRawPtr()
321 temps.Exclude(reg_x(dst.AsXRegister()), reg_x(base.AsXRegister())); in LoadRawPtr()
[all …]
/art/runtime/native/
Dlibcore_util_CharsetUtils.cc126 jchar* dst = &chars[0]; in CharsetUtils_asciiBytesToChars() local
130 *dst++ = (ch <= 0x7f) ? ch : REPLACEMENT_CHAR; in CharsetUtils_asciiBytesToChars()
146 jchar* dst = &chars[0]; in CharsetUtils_isoLatin1BytesToChars() local
148 *dst++ = static_cast<jchar>(*src++ & 0xff); in CharsetUtils_isoLatin1BytesToChars()
172 jbyte* dst = &bytes[0]; in charsToBytes() local
178 *dst++ = static_cast<jbyte>(ch); in charsToBytes()

123