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Searched refs:AArch64 (Results 1 – 25 of 171) sorted by relevance

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/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h32 case AArch64::X0: return AArch64::W0; in getWRegFromXReg()
33 case AArch64::X1: return AArch64::W1; in getWRegFromXReg()
34 case AArch64::X2: return AArch64::W2; in getWRegFromXReg()
35 case AArch64::X3: return AArch64::W3; in getWRegFromXReg()
36 case AArch64::X4: return AArch64::W4; in getWRegFromXReg()
37 case AArch64::X5: return AArch64::W5; in getWRegFromXReg()
38 case AArch64::X6: return AArch64::W6; in getWRegFromXReg()
39 case AArch64::X7: return AArch64::W7; in getWRegFromXReg()
40 case AArch64::X8: return AArch64::W8; in getWRegFromXReg()
41 case AArch64::X9: return AArch64::W9; in getWRegFromXReg()
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/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp256 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
257 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
258 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
259 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
260 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
261 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
262 AArch64::Q30, AArch64::Q31
285 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
286 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
287 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
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/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp58 if (Opcode == AArch64::SYSxt) in printInst()
65 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri || in printInst()
66 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) { in printInst()
72 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri); in printInst()
73 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri); in printInst()
115 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { in printInst()
118 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f && in printInst()
122 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) { in printInst()
125 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) { in printInst()
128 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) { in printInst()
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/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp36 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP), in AArch64InstrInfo()
46 if (MI.getOpcode() == AArch64::INLINEASM) in GetInstSizeInBytes()
70 case AArch64::Bcc: in parseCondBranch()
74 case AArch64::CBZW: in parseCondBranch()
75 case AArch64::CBZX: in parseCondBranch()
76 case AArch64::CBNZW: in parseCondBranch()
77 case AArch64::CBNZX: in parseCondBranch()
83 case AArch64::TBZW: in parseCondBranch()
84 case AArch64::TBZX: in parseCondBranch()
85 case AArch64::TBNZW: in parseCondBranch()
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DAArch64LoadStoreOptimizer.cpp186 case AArch64::LDRBBui: in getBitExtrOpcode()
187 case AArch64::LDURBBi: in getBitExtrOpcode()
188 case AArch64::LDRHHui: in getBitExtrOpcode()
189 case AArch64::LDURHHi: in getBitExtrOpcode()
190 return AArch64::UBFMWri; in getBitExtrOpcode()
191 case AArch64::LDRSBWui: in getBitExtrOpcode()
192 case AArch64::LDURSBWi: in getBitExtrOpcode()
193 case AArch64::LDRSHWui: in getBitExtrOpcode()
194 case AArch64::LDURSHWi: in getBitExtrOpcode()
195 return AArch64::SBFMWri; in getBitExtrOpcode()
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DAArch64PBQPRegAlloc.cpp38 return AArch64::FPR32RegClass.contains(reg) || in isFPReg()
39 AArch64::FPR64RegClass.contains(reg) || in isFPReg()
40 AArch64::FPR128RegClass.contains(reg); in isFPReg()
48 case AArch64::S1: in isOdd()
49 case AArch64::S3: in isOdd()
50 case AArch64::S5: in isOdd()
51 case AArch64::S7: in isOdd()
52 case AArch64::S9: in isOdd()
53 case AArch64::S11: in isOdd()
54 case AArch64::S13: in isOdd()
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DAArch64RegisterBankInfo.cpp29 : RegisterBankInfo(AArch64::NumRegisterBanks) { in AArch64RegisterBankInfo()
31 createRegisterBank(AArch64::GPRRegBankID, "GPR"); in AArch64RegisterBankInfo()
34 addRegBankCoverage(AArch64::GPRRegBankID, AArch64::GPR64allRegClassID, TRI); in AArch64RegisterBankInfo()
35 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
37 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) && in AArch64RegisterBankInfo()
42 createRegisterBank(AArch64::FPRRegBankID, "FPR"); in AArch64RegisterBankInfo()
45 addRegBankCoverage(AArch64::FPRRegBankID, AArch64::QQQQRegClassID, TRI); in AArch64RegisterBankInfo()
46 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
48 assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) && in AArch64RegisterBankInfo()
50 assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) && in AArch64RegisterBankInfo()
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DAArch64CallingConvention.h28 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
29 AArch64::X3, AArch64::X4, AArch64::X5,
30 AArch64::X6, AArch64::X7};
31 static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
32 AArch64::H3, AArch64::H4, AArch64::H5,
33 AArch64::H6, AArch64::H7};
34 static const MCPhysReg SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
35 AArch64::S3, AArch64::S4, AArch64::S5,
36 AArch64::S6, AArch64::S7};
37 static const MCPhysReg DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
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DAArch64ExpandPseudoInsts.cpp120 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri)) in tryOrrMovk()
122 .addReg(AArch64::XZR) in tryOrrMovk()
130 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi)) in tryOrrMovk()
187 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri)) in tryToreplicateChunks()
189 .addReg(AArch64::XZR) in tryToreplicateChunks()
207 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi)) in tryToreplicateChunks()
232 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi)) in tryToreplicateChunks()
370 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri)) in trySequenceOfOnes()
372 .addReg(AArch64::XZR) in trySequenceOfOnes()
381 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi)) in trySequenceOfOnes()
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DAArch64ISelDAGToDAG.cpp485 MLAOpc = AArch64::MLAv4i16_indexed; in tryMLAV64LaneV128()
488 MLAOpc = AArch64::MLAv8i16_indexed; in tryMLAV64LaneV128()
491 MLAOpc = AArch64::MLAv2i32_indexed; in tryMLAV64LaneV128()
494 MLAOpc = AArch64::MLAv4i32_indexed; in tryMLAV64LaneV128()
523 SMULLOpc = AArch64::SMULLv4i16_indexed; in tryMULLV64LaneV128()
526 SMULLOpc = AArch64::SMULLv2i32_indexed; in tryMULLV64LaneV128()
534 SMULLOpc = AArch64::UMULLv4i16_indexed; in tryMULLV64LaneV128()
537 SMULLOpc = AArch64::UMULLv2i32_indexed; in tryMULLV64LaneV128()
556 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); in narrowIfNeeded()
765 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); in Widen()
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DAArch64BranchRelaxation.cpp239 BuildMI(OrigBB, DebugLoc(), TII->get(AArch64::B)).addMBB(NewBB); in splitBlockBeforeInstr()
288 case AArch64::TBZW: in isConditionalBranch()
289 case AArch64::TBNZW: in isConditionalBranch()
290 case AArch64::TBZX: in isConditionalBranch()
291 case AArch64::TBNZX: in isConditionalBranch()
292 case AArch64::CBZW: in isConditionalBranch()
293 case AArch64::CBNZW: in isConditionalBranch()
294 case AArch64::CBZX: in isConditionalBranch()
295 case AArch64::CBNZX: in isConditionalBranch()
296 case AArch64::Bcc: in isConditionalBranch()
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DAArch64RegisterInfo.cpp38 : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {} in AArch64RegisterInfo()
121 Reserved.set(AArch64::SP); in getReservedRegs()
122 Reserved.set(AArch64::XZR); in getReservedRegs()
123 Reserved.set(AArch64::WSP); in getReservedRegs()
124 Reserved.set(AArch64::WZR); in getReservedRegs()
127 Reserved.set(AArch64::FP); in getReservedRegs()
128 Reserved.set(AArch64::W29); in getReservedRegs()
132 Reserved.set(AArch64::X18); // Platform register in getReservedRegs()
133 Reserved.set(AArch64::W18); in getReservedRegs()
137 Reserved.set(AArch64::X19); in getReservedRegs()
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DAArch64ConditionalCompares.cpp257 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR) in isDeadDef()
282 case AArch64::CBZW: in parseCond()
283 case AArch64::CBZX: in parseCond()
287 case AArch64::CBNZW: in parseCond()
288 case AArch64::CBNZX: in parseCond()
300 if (!I->readsRegister(AArch64::NZCV)) { in findConvertibleCompare()
302 case AArch64::CBZW: in findConvertibleCompare()
303 case AArch64::CBZX: in findConvertibleCompare()
304 case AArch64::CBNZW: in findConvertibleCompare()
305 case AArch64::CBNZX: in findConvertibleCompare()
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DAArch64FastISel.cpp323 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); in fastMaterializeAlloca()
324 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri), in fastMaterializeAlloca()
343 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass in materializeInt()
344 : &AArch64::GPR32RegClass; in materializeInt()
345 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in materializeInt()
369 unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi; in materializeFP()
375 unsigned Opc1 = Is64Bit ? AArch64::MOVi64imm : AArch64::MOVi32imm; in materializeFP()
377 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in materializeFP()
398 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass); in materializeFP()
399 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP), in materializeFP()
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DAArch64FrameLowering.cpp191 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, Amount, TII); in eliminateCallFramePseudoInstr()
197 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, -CalleePopAmount, in eliminateCallFramePseudoInstr()
246 return AArch64::X9; in findScratchNonCalleeSaveRegister()
261 if (LiveRegs.available(MRI, AArch64::X9)) in findScratchNonCalleeSaveRegister()
262 return AArch64::X9; in findScratchNonCalleeSaveRegister()
264 for (unsigned Reg : AArch64::GPR64RegClass) { in findScratchNonCalleeSaveRegister()
268 return AArch64::NoRegister; in findScratchNonCalleeSaveRegister()
283 return findScratchNonCalleeSaveRegister(TmpMBB) != AArch64::NoRegister; in canUseAsPrologue()
328 case AArch64::STPXi: in convertCalleeSaveRestoreToSPPrePostIncDec()
329 NewOpc = AArch64::STPXpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
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DAArch64AsmPrinter.cpp237 RegToPrint, isVector ? AArch64::vreg : AArch64::NoRegAltName); in printAsmRegInClass()
263 unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR; in PrintAsmOperand()
278 RC = &AArch64::FPR8RegClass; in PrintAsmOperand()
281 RC = &AArch64::FPR16RegClass; in PrintAsmOperand()
284 RC = &AArch64::FPR32RegClass; in PrintAsmOperand()
287 RC = &AArch64::FPR64RegClass; in PrintAsmOperand()
290 RC = &AArch64::FPR128RegClass; in PrintAsmOperand()
308 if (AArch64::GPR32allRegClass.contains(Reg) || in PrintAsmOperand()
309 AArch64::GPR64allRegClass.contains(Reg)) in PrintAsmOperand()
313 return printAsmRegInClass(MO, &AArch64::FPR128RegClass, true /* vector */, in PrintAsmOperand()
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DAArch64ConditionOptimizer.cpp143 if (I->getOpcode() != AArch64::Bcc) in findSuitableCompare()
148 if (SuccBB->isLiveIn(AArch64::NZCV)) in findSuitableCompare()
156 if (I->readsRegister(AArch64::NZCV)) in findSuitableCompare()
160 case AArch64::SUBSWri: in findSuitableCompare()
161 case AArch64::SUBSXri: in findSuitableCompare()
163 case AArch64::ADDSWri: in findSuitableCompare()
164 case AArch64::ADDSXri: { in findSuitableCompare()
184 case AArch64::FCMPDri: in findSuitableCompare()
185 case AArch64::FCMPSri: in findSuitableCompare()
186 case AArch64::FCMPESri: in findSuitableCompare()
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DAArch64AdvSIMDScalarPass.cpp117 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
118 return AArch64::GPR64RegClass.contains(Reg); in isGPR64()
124 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
126 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
127 SubReg == AArch64::dsub); in isFPR64()
129 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) || in isFPR64()
130 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub); in isFPR64()
140 if (MI->getOpcode() == AArch64::FMOVDXr || in getSrcFromCopy()
141 MI->getOpcode() == AArch64::FMOVXDr) in getSrcFromCopy()
145 if (MI->getOpcode() == AArch64::UMOVvi64 && MI->getOperand(2).getImm() == 0) { in getSrcFromCopy()
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DAArch64A53Fix835769.cpp43 case AArch64::PRFMl: in isFirstInstructionInSequence()
44 case AArch64::PRFMroW: in isFirstInstructionInSequence()
45 case AArch64::PRFMroX: in isFirstInstructionInSequence()
46 case AArch64::PRFMui: in isFirstInstructionInSequence()
47 case AArch64::PRFUMi: in isFirstInstructionInSequence()
62 case AArch64::MSUBXrrr: in isSecondInstructionInSequence()
63 case AArch64::MADDXrrr: in isSecondInstructionInSequence()
64 case AArch64::SMADDLrrr: in isSecondInstructionInSequence()
65 case AArch64::SMSUBLrrr: in isSecondInstructionInSequence()
66 case AArch64::UMADDLrrr: in isSecondInstructionInSequence()
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DAArch64CollectLOH.cpp304 bool IsADRP = MI.getOpcode() == AArch64::ADRP; in initReachingDef()
507 case AArch64::ADRP: in canDefBePartOfLOH()
509 case AArch64::ADDXri: in canDefBePartOfLOH()
520 case AArch64::LDRXui: in canDefBePartOfLOH()
539 case AArch64::STRBBui: in isCandidateStore()
540 case AArch64::STRHHui: in isCandidateStore()
541 case AArch64::STRBui: in isCandidateStore()
542 case AArch64::STRHui: in isCandidateStore()
543 case AArch64::STRWui: in isCandidateStore()
544 case AArch64::STRXui: in isCandidateStore()
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/external/swiftshader/third_party/llvm-subzero/include/llvm/Support/
DAArch64TargetParser.def20 ARMBuildAttrs::CPUArch::v8_A, FK_NONE, AArch64::AEK_NONE)
23 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
24 AArch64::AEK_SIMD | AArch64::AEK_LSE))
27 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
28 AArch64::AEK_SIMD | AArch64::AEK_LSE))
31 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
32 AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE))
39 AARCH64_ARCH_EXT_NAME("invalid", AArch64::AEK_INVALID, nullptr, nullptr)
40 AARCH64_ARCH_EXT_NAME("none", AArch64::AEK_NONE, nullptr, nullptr)
41 AARCH64_ARCH_EXT_NAME("crc", AArch64::AEK_CRC, "+crc", "-crc")
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/external/llvm/include/llvm/Support/
DAArch64TargetParser.def21 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
22 AArch64::AEK_SIMD | AArch64::AEK_FP16 | AArch64::AEK_PROFILE))
25 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
26 AArch64::AEK_SIMD | AArch64::AEK_FP16 | AArch64::AEK_PROFILE))
29 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
30 AArch64::AEK_SIMD | AArch64::AEK_FP16 | AArch64::AEK_PROFILE |
31 AArch64::AEK_RAS))
38 AARCH64_ARCH_EXT_NAME("invalid", AArch64::AEK_INVALID, nullptr, nullptr)
39 AARCH64_ARCH_EXT_NAME("none", AArch64::AEK_NONE, nullptr, nullptr)
40 AARCH64_ARCH_EXT_NAME("crc", AArch64::AEK_CRC, "+crc", "-crc")
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/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AsmBackend.cpp40 return AArch64::NumTargetFixupKinds; in getNumFixupKinds()
44 const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = { in getFixupKindInfo()
100 case AArch64::fixup_aarch64_tlsdesc_call: in getFixupKindNumBytes()
107 case AArch64::fixup_aarch64_movw: in getFixupKindNumBytes()
110 case AArch64::fixup_aarch64_pcrel_branch14: in getFixupKindNumBytes()
111 case AArch64::fixup_aarch64_add_imm12: in getFixupKindNumBytes()
112 case AArch64::fixup_aarch64_ldst_imm12_scale1: in getFixupKindNumBytes()
113 case AArch64::fixup_aarch64_ldst_imm12_scale2: in getFixupKindNumBytes()
114 case AArch64::fixup_aarch64_ldst_imm12_scale4: in getFixupKindNumBytes()
115 case AArch64::fixup_aarch64_ldst_imm12_scale8: in getFixupKindNumBytes()
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/external/swiftshader/third_party/llvm-subzero/lib/Support/
DTargetParser.cpp24 using namespace AArch64;
82 ArchNames<AArch64::ArchKind> AArch64ARCHNames[] = {
85 sizeof(SUB_ARCH) - 1, ARCH_FPU, ARCH_BASE_EXT, AArch64::ArchKind::ID, ARCH_ATTR},
144 CpuNames<AArch64::ArchKind> AArch64CPUNames[] = {
146 { NAME, sizeof(NAME) - 1, AArch64::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT },
393 StringRef llvm::AArch64::getFPUName(unsigned FPUKind) { in getFPUName()
397 unsigned llvm::AArch64::getFPUVersion(unsigned FPUKind) { in getFPUVersion()
401 unsigned llvm::AArch64::getFPUNeonSupportLevel(unsigned FPUKind) { in getFPUNeonSupportLevel()
405 unsigned llvm::AArch64::getFPURestriction(unsigned FPUKind) { in getFPURestriction()
409 unsigned llvm::AArch64::getDefaultFPU(StringRef CPU, unsigned ArchKind) { in getDefaultFPU()
[all …]
/external/llvm/lib/Support/
DTargetParser.cpp24 using namespace AArch64;
386 StringRef llvm::AArch64::getFPUName(unsigned FPUKind) { in getFPUName()
390 unsigned llvm::AArch64::getFPUVersion(unsigned FPUKind) { in getFPUVersion()
394 unsigned llvm::AArch64::getFPUNeonSupportLevel(unsigned FPUKind) { in getFPUNeonSupportLevel()
398 unsigned llvm::AArch64::getFPURestriction(unsigned FPUKind) { in getFPURestriction()
402 unsigned llvm::AArch64::getDefaultFPU(StringRef CPU, unsigned ArchKind) { in getDefaultFPU()
413 unsigned llvm::AArch64::getDefaultExtensions(StringRef CPU, unsigned ArchKind) { in getDefaultExtensions()
421 .Default(AArch64::AEK_INVALID); in getDefaultExtensions()
424 bool llvm::AArch64::getExtensionFeatures(unsigned Extensions, in getExtensionFeatures()
427 if (Extensions == AArch64::AEK_INVALID) in getExtensionFeatures()
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