/external/mesa3d/src/mesa/drivers/dri/i965/ |
D | brw_misc_state.c | 55 BEGIN_BATCH(4); in upload_drawing_rect() 83 BEGIN_BATCH(1); in upload_pipelined_state_pointers() 88 BEGIN_BATCH(7); in upload_pipelined_state_pointers() 603 BEGIN_BATCH(len); in brw_emit_depth_stencil_hiz() 649 BEGIN_BATCH(3); in brw_emit_depth_stencil_hiz() 657 BEGIN_BATCH(3); in brw_emit_depth_stencil_hiz() 666 BEGIN_BATCH(3); in brw_emit_depth_stencil_hiz() 679 BEGIN_BATCH(3); in brw_emit_depth_stencil_hiz() 696 BEGIN_BATCH(2); in brw_emit_depth_stencil_hiz() 727 BEGIN_BATCH(33); in upload_polygon_stipple() [all …]
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D | gen8_draw_upload.c | 96 BEGIN_BATCH(2); in gen8_emit_vertices() 101 BEGIN_BATCH(3); in gen8_emit_vertices() 107 BEGIN_BATCH(2); in gen8_emit_vertices() 137 BEGIN_BATCH(3); in gen8_emit_vertices() 161 BEGIN_BATCH(1 + 4 * nr_buffers); in gen8_emit_vertices() 198 BEGIN_BATCH(1 + nr_elements * 2); in gen8_emit_vertices() 338 BEGIN_BATCH(3); in gen8_emit_vertices() 348 BEGIN_BATCH(3); in gen8_emit_vertices() 376 BEGIN_BATCH(5); in gen8_emit_index_buffer() 397 BEGIN_BATCH(2); in gen8_emit_vf_topology()
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D | gen8_depth_state.c | 63 BEGIN_BATCH(8); in emit_depth_packets() 85 BEGIN_BATCH(5); in emit_depth_packets() 94 BEGIN_BATCH(5); in emit_depth_packets() 104 BEGIN_BATCH(5); in emit_depth_packets() 112 BEGIN_BATCH(5); in emit_depth_packets() 136 BEGIN_BATCH(3); in emit_depth_packets() 350 BEGIN_BATCH(3); in gen8_write_pma_stall_bits() 459 BEGIN_BATCH(4); in gen8_hiz_exec() 500 BEGIN_BATCH(5); in gen8_hiz_exec() 518 BEGIN_BATCH(5); in gen8_hiz_exec()
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D | gen7_misc_state.c | 103 BEGIN_BATCH(7); in gen7_emit_depth_stencil_hiz() 142 BEGIN_BATCH(3); in gen7_emit_depth_stencil_hiz() 151 BEGIN_BATCH(3); in gen7_emit_depth_stencil_hiz() 163 BEGIN_BATCH(3); in gen7_emit_depth_stencil_hiz() 172 BEGIN_BATCH(3); in gen7_emit_depth_stencil_hiz() 193 BEGIN_BATCH(3); in gen7_emit_depth_stencil_hiz()
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D | brw_compute.c | 57 BEGIN_BATCH(7); in prepare_indirect_gpgpu_walker() 73 BEGIN_BATCH(1); in prepare_indirect_gpgpu_walker() 86 BEGIN_BATCH(1); in prepare_indirect_gpgpu_walker() 99 BEGIN_BATCH(1); in prepare_indirect_gpgpu_walker() 107 BEGIN_BATCH(1); in prepare_indirect_gpgpu_walker() 145 BEGIN_BATCH(dwords); in brw_emit_gpgpu_walker() 169 BEGIN_BATCH(2); in brw_emit_gpgpu_walker()
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D | gen6_depth_state.c | 110 BEGIN_BATCH(7); in gen6_emit_depth_stencil_hiz() 174 BEGIN_BATCH(3); in gen6_emit_depth_stencil_hiz() 182 BEGIN_BATCH(3); in gen6_emit_depth_stencil_hiz() 210 BEGIN_BATCH(3); in gen6_emit_depth_stencil_hiz() 223 BEGIN_BATCH(3); in gen6_emit_depth_stencil_hiz() 239 BEGIN_BATCH(2); in gen6_emit_depth_stencil_hiz()
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D | brw_pipe_control.c | 131 BEGIN_BATCH(6); in brw_emit_pipe_control_flush() 153 BEGIN_BATCH(5); in brw_emit_pipe_control_flush() 161 BEGIN_BATCH(4); in brw_emit_pipe_control_flush() 187 BEGIN_BATCH(6); in brw_emit_pipe_control_write() 203 BEGIN_BATCH(5); in brw_emit_pipe_control_write() 212 BEGIN_BATCH(4); in brw_emit_pipe_control_write()
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D | intel_batchbuffer.c | 260 BEGIN_BATCH(2); in brw_finish_batch() 506 BEGIN_BATCH(4 * size); in load_sized_register_mem() 514 BEGIN_BATCH(3 * size); in load_sized_register_mem() 554 BEGIN_BATCH(4); in brw_store_register_mem32() 561 BEGIN_BATCH(3); in brw_store_register_mem32() 583 BEGIN_BATCH(8); in brw_store_register_mem64() 594 BEGIN_BATCH(6); in brw_store_register_mem64() 615 BEGIN_BATCH(3); in brw_load_register_imm32() 630 BEGIN_BATCH(5); in brw_load_register_imm64() 647 BEGIN_BATCH(3); in brw_load_register_reg() [all …]
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D | hsw_sol.c | 107 BEGIN_BATCH(9); in tally_prims_written() 130 BEGIN_BATCH(5); in tally_prims_written() 139 BEGIN_BATCH(9); in tally_prims_written() 175 BEGIN_BATCH(1 + 2 * BRW_MAX_XFB_STREAMS); in hsw_begin_transform_feedback() 209 BEGIN_BATCH(3); in hsw_pause_transform_feedback() 237 BEGIN_BATCH(3); in hsw_resume_transform_feedback()
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D | gen6_gs_state.c | 73 BEGIN_BATCH(7); in upload_gs_state_for_tf() 106 BEGIN_BATCH(5); in upload_gs_state() 114 BEGIN_BATCH(5); in upload_gs_state() 130 BEGIN_BATCH(7); in upload_gs_state() 186 BEGIN_BATCH(7); in upload_gs_state()
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D | hsw_queryobj.c | 76 BEGIN_BATCH(1 + ARRAY_SIZE(maths)); in mult_gpr0_by_80() 101 BEGIN_BATCH(1 + ARRAY_SIZE(maths)); in keep_gpr0_lower_n_bits() 132 BEGIN_BATCH(batch_len); in shl_gpr0_by_30_bits() 180 BEGIN_BATCH(1 + ARRAY_SIZE(maths)); in gpr0_to_bool() 240 BEGIN_BATCH(5); in hsw_result_to_gpr0() 312 BEGIN_BATCH(1); in set_predicate() 334 BEGIN_BATCH(dwords * cmd_size); in store_query_result_reg()
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D | brw_binding_tables.c | 136 BEGIN_BATCH(2); in brw_upload_binding_table() 302 BEGIN_BATCH(3); in gen7_edit_hw_binding_table_entry() 326 BEGIN_BATCH(num_surfaces + 2); in gen7_update_binding_table_from_array() 357 BEGIN_BATCH(pkt_len); in gen7_disable_hw_binding_tables() 411 BEGIN_BATCH(pkt_len); in gen7_enable_hw_binding_tables() 455 BEGIN_BATCH(6); in gen4_upload_binding_table_pointers() 485 BEGIN_BATCH(4); in gen6_upload_binding_table_pointers()
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D | gen6_vs_state.c | 97 BEGIN_BATCH(5); in upload_vs_state() 105 BEGIN_BATCH(5); in upload_vs_state() 123 BEGIN_BATCH(6); in upload_vs_state()
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D | gen7_te_state.c | 39 BEGIN_BATCH(4); in upload_te_state() 49 BEGIN_BATCH(4); in upload_te_state()
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D | gen8_multisample_state.c | 40 BEGIN_BATCH(2); in gen8_emit_3dstate_multisample() 52 BEGIN_BATCH(9); in gen8_emit_3dstate_sample_pattern()
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D | gen8_sf_state.c | 113 BEGIN_BATCH(sbe_cmd_length); in upload_sbe() 124 BEGIN_BATCH(11); in upload_sbe() 206 BEGIN_BATCH(4); in upload_sf() 328 BEGIN_BATCH(5); in upload_raster()
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D | gen7_sol_state.c | 63 BEGIN_BATCH(4); in upload_3dstate_so_buffers() 81 BEGIN_BATCH(4); in upload_3dstate_so_buffers() 194 BEGIN_BATCH(max_decls * 2 + 3); in gen7_upload_3dstate_so_decl_list() 297 BEGIN_BATCH(dwords); in upload_3dstate_streamout() 558 BEGIN_BATCH(3); in gen7_pause_transform_feedback() 587 BEGIN_BATCH(3); in gen7_resume_transform_feedback()
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D | gen8_hs_state.c | 42 BEGIN_BATCH(9); in gen8_upload_hs_state() 69 BEGIN_BATCH(9); in gen8_upload_hs_state()
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D | gen8_sol_state.c | 57 BEGIN_BATCH(8); in gen8_upload_3dstate_so_buffers() 77 BEGIN_BATCH(8); in gen8_upload_3dstate_so_buffers()
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D | gen6_cc.c | 229 BEGIN_BATCH(4); in gen6_upload_blend_state() 236 BEGIN_BATCH(2); in gen6_upload_blend_state() 284 BEGIN_BATCH(4); in gen6_upload_color_calc_state() 291 BEGIN_BATCH(2); in gen6_upload_color_calc_state()
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D | gen8_ds_state.c | 46 BEGIN_BATCH(ds_pkt_len); in gen8_upload_ds_state() 85 BEGIN_BATCH(ds_pkt_len); in gen8_upload_ds_state()
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/external/mesa3d/src/gallium/drivers/i915/ |
D | i915_blit.c | 74 if (!BEGIN_BATCH(6)) { in i915_fill_blit() 76 assert(BEGIN_BATCH(6)); in i915_fill_blit() 146 if (!BEGIN_BATCH(8)) { in i915_copy_blit() 148 assert(BEGIN_BATCH(8)); in i915_copy_blit()
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D | i915_clear.c | 124 if (!BEGIN_BATCH(1 + 2*(7 + 7))) { in i915_clear_emit() 130 assert(BEGIN_BATCH(1 + 2*(7 + 7))); in i915_clear_emit() 175 if (!BEGIN_BATCH(1 + 7 + 7)) { in i915_clear_emit() 181 assert(BEGIN_BATCH(1 + 7 + 7)); in i915_clear_emit()
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/external/mesa3d/src/mesa/drivers/dri/radeon/ |
D | radeon_ioctl.c | 101 BEGIN_BATCH(6); in radeonEmitScissor() 112 BEGIN_BATCH(2); in radeonEmitScissor() 135 BEGIN_BATCH(8); in radeonEmitVbufPrim() 154 BEGIN_BATCH(4); in radeonEmitVbufPrim() 237 BEGIN_BATCH(2+ELTS_BUFSZ(align_min_nr)/4); in radeonAllocEltsOpenEnded() 247 BEGIN_BATCH(ELTS_BUFSZ(align_min_nr)/4); in radeonAllocEltsOpenEnded() 289 BEGIN_BATCH(7); in radeonEmitVertexAOS() 320 BEGIN_BATCH(sz+2+(nr * 2)); in radeonEmitAOS()
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/external/mesa3d/src/mesa/drivers/dri/r200/ |
D | r200_blit.c | 99 BEGIN_BATCH(14); in emit_vtx_state() 167 BEGIN_BATCH(10); in emit_tx_setup() 188 BEGIN_BATCH(10); in emit_tx_setup() 218 BEGIN_BATCH(34); in emit_tx_setup() 291 BEGIN_BATCH(18); in emit_tx_setup() 359 BEGIN_BATCH(22); in emit_cb_setup() 449 BEGIN_BATCH(14); in emit_draw_packet()
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