/external/llvm/test/MC/AArch64/ |
D | arm64-arithmetic-encoding.s | 569 CSEL W16, W7, W27, EQ 570 CSEL W15, W6, W26, NE 571 CSEL W14, W5, W25, CS 572 CSEL W13, W4, W24, HS 578 CSEL X7, X7, X3, VC 579 CSEL X6, X7, X4, HI 580 CSEL X5, X6, X5, LS 581 CSEL X4, X5, X6, GE
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
D | brw_vec4_builder.h | 408 ALU3(CSEL) in ALU2_ACC()
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D | brw_fs_builder.h | 462 ALU3(CSEL) in ALU2_ACC()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.cpp | 743 case AArch64ISD::CSEL: { in computeKnownBitsForTargetNode() 842 case AArch64ISD::CSEL: return "AArch64ISD::CSEL"; in getTargetNodeName() 1788 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal, in LowerXOR() 1850 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal, in LowerXALUO() 3888 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp); in LowerSETCC() 3907 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp); in LowerSETCC() 3917 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp); in LowerSETCC() 3920 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp); in LowerSETCC() 3952 unsigned Opcode = AArch64ISD::CSEL; in LowerSELECT_CC() 4027 if (Opcode != AArch64ISD::CSEL) { in LowerSELECT_CC() [all …]
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D | AArch64ISelLowering.h | 43 CSEL, enumerator
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D | AArch64SchedCyclone.td | 145 // CSEL,CSINC,CSINV,CSNEG
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D | AArch64SchedKryoDetails.td | 544 (instregex "CSEL(W|X)r")>;
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D | AArch64InstrInfo.td | 172 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>; 1112 defm CSEL : CondSelect<0, 0b00, "csel">; 2685 // CSEL instructions providing f128 types need to be handled by a
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/external/v8/src/arm64/ |
D | constants-arm64.h | 919 CSEL = CSEL_w, enumerator
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D | assembler-arm64.cc | 1333 ConditionalSelect(rd, rn, rm, cond, CSEL); in csel()
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/external/vixl/src/aarch64/ |
D | constants-aarch64.h | 1009 CSEL = CSEL_w, enumerator
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D | assembler-aarch64.cc | 640 ConditionalSelect(rd, rn, rm, cond, CSEL); in csel()
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/external/vixl/doc/aarch64/ |
D | supported-instructions-aarch64.md | 395 ### CSEL ### subsection
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