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Searched refs:CompleteModel (Results 1 – 25 of 31) sorted by relevance

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/external/llvm/include/llvm/MC/
DMCSchedule.h185 bool CompleteModel; member
203 bool isComplete() const { return CompleteModel; } in isComplete()
/external/llvm/lib/Target/Lanai/
DLanaiSchedule.td37 let CompleteModel = 0;
/external/llvm/lib/Target/AMDGPU/
DSISchedule.td49 let CompleteModel = 0;
/external/llvm/lib/Target/PowerPC/
DPPCScheduleA2.td168 let CompleteModel = 0;
DPPCScheduleG5.td126 let CompleteModel = 0;
DPPCScheduleE500mc.td318 let CompleteModel = 0;
DPPCScheduleE5500.td378 let CompleteModel = 0;
DPPCScheduleP7.td393 let CompleteModel = 0;
DPPCScheduleP8.td402 let CompleteModel = 0;
DPPCSchedule440.td604 let CompleteModel = 0;
/external/llvm/lib/Target/Hexagon/
DHexagonScheduleV55.td166 let CompleteModel = 0;
DHexagonScheduleV4.td202 let CompleteModel = 0;
DHexagonScheduleV60.td306 let CompleteModel = 0;
/external/llvm/lib/Target/AArch64/
DAArch64SchedKryo.td29 let CompleteModel = 1;
DAArch64SchedA53.td28 let CompleteModel = 1;
DAArch64SchedM1.td26 let CompleteModel = 0; // Use the default model otherwise.
/external/llvm/lib/Target/X86/
DX86ScheduleSLM.td29 let CompleteModel = 0;
DX86SchedSandyBridge.td29 let CompleteModel = 0;
DX86ScheduleBtVer2.td28 let CompleteModel = 0;
DX86ScheduleAtom.td547 let CompleteModel = 0;
DX86Schedule.td646 let CompleteModel = 0;
/external/llvm/utils/TableGen/
DSubtargetEmitter.cpp1175 bool CompleteModel = in EmitProcessorModels() local
1178 OS << " " << (CompleteModel ? "true" : "false") << ", // " in EmitProcessorModels()
/external/llvm/include/llvm/Target/
DTargetSchedule.td100 bit CompleteModel = 1;
121 let CompleteModel = 0;
/external/llvm/lib/Target/Mips/
DMipsScheduleP5600.td16 let CompleteModel = 0;
/external/llvm/lib/Target/ARM/
DARMScheduleA8.td1072 let CompleteModel = 0;

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