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/external/llvm/test/CodeGen/X86/
Dabi-isel.ll58 ; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), [[RCX:%r..]]
59 ; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]])
87 ; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r..]]
88 ; DARWIN-64-STATIC-NEXT: movl [[EAX]], ([[RCX]])
94 ; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r..]]
95 ; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], ([[RCX]])
101 ; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r..]]
102 ; DARWIN-64-PIC-NEXT: movl [[EAX]], ([[RCX]])
130 ; LINUX-64-PIC-NEXT: movq xdst@GOTPCREL(%rip), [[RCX:%r.x]]
131 ; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]])
[all …]
Dfp-stack-O0.ll11 ; CHECK-NEXT: movq %rsp, [[RCX:%r..]]
14 ; CHECK-NEXT: fstpt 16([[RCX]])
16 ; CHECK-NEXT: fstpt ([[RCX]])
Dor-address.ll50 ; CHECK: movl %{{.*}}, (%[[RDI:...]],%[[RCX:...]],4)
51 ; CHECK: movl %{{.*}}, 8(%[[RDI]],%[[RCX]],4)
52 ; CHECK: movl %{{.*}}, 4(%[[RDI]],%[[RCX]],4)
53 ; CHECK: movl %{{.*}}, 12(%[[RDI]],%[[RCX]],4)
D2009-09-19-earlyclobber.ll4 ; Registers other than RAX, RCX are OK, but they must be different.
Dipra-inline-asm.ll14 ; CHECK: foo Clobbered Registers: AH AL AX CH CL CX DI DIL EAX ECX EDI RAX RCX RDI
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dabi-isel.ll58 ; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), [[RCX:%r..]]
59 ; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]])
87 ; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r..]]
88 ; DARWIN-64-STATIC-NEXT: movl [[EAX]], ([[RCX]])
94 ; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r..]]
95 ; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], ([[RCX]])
101 ; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r..]]
102 ; DARWIN-64-PIC-NEXT: movl [[EAX]], ([[RCX]])
130 ; LINUX-64-PIC-NEXT: movq xdst@GOTPCREL(%rip), [[RCX:%r.x]]
131 ; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]])
[all …]
Dfp-stack-O0.ll11 ; CHECK-NEXT: movq %rsp, [[RCX:%r..]]
14 ; CHECK-NEXT: fstpt 16([[RCX]])
16 ; CHECK-NEXT: fstpt ([[RCX]])
Dor-address.ll50 ; CHECK: movl %{{.*}}, (%[[RDI:...]],%[[RCX:...]],4)
51 ; CHECK: movl %{{.*}}, 8(%[[RDI]],%[[RCX]],4)
52 ; CHECK: movl %{{.*}}, 4(%[[RDI]],%[[RCX]],4)
53 ; CHECK: movl %{{.*}}, 12(%[[RDI]],%[[RCX]],4)
D2009-09-19-earlyclobber.ll4 ; Registers other than RAX, RCX are OK, but they must be different.
/external/llvm/lib/Target/X86/
DX86SelectionDAGInfo.cpp57 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI, in EmitTargetCodeForMemset()
153 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX, in EmitTargetCodeForMemset()
171 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : X86::ECX, in EmitTargetCodeForMemset()
224 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RSI, X86::RDI, in EmitTargetCodeForMemcpy()
247 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX, in EmitTargetCodeForMemcpy()
DX86CallingConv.td41 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
204 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>,
233 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
312 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
374 RDI, RSI, RDX, RCX, R8, R9,
415 // Do not pass the sret argument in RCX, the Win64 thiscall calling
416 // convention requires "this" to be passed in RCX.
421 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
427 [RCX , RDX , R8 , R9 ]>>,
476 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
[all …]
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp109 X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBP, X86::RSP, in initLLVMToSEHAndCVRegMapping()
297 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegisterOrZero()
309 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegisterOrZero()
346 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegisterOrZero()
382 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegisterOrZero()
418 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegisterOrZero()
419 return X86::RCX; in getX86SubSuperRegisterOrZero()
/external/libunwind/src/x86_64/
Dinit.h51 c->dwarf.loc[RCX] = REG_INIT_LOC(c, rcx, RCX); in common_init()
Dunwind_i.h41 #define RCX 2 macro
DGos-freebsd.c113 c->dwarf.loc[RCX] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_RCX, 0); in unw_handle_signal_frame()
133 c->dwarf.loc[RCX] = c->dwarf.loc[R10]; in unw_handle_signal_frame()
/external/llvm/test/MC/X86/
Dintel-syntax.s25 mov RCX, QWORD PTR [0]
29 mov BYTE PTR [RDX + RCX], DIL
31 movzx EDI, WORD PTR [RCX + 2]
453 xchg RAX, RCX
454 xchg RCX, RAX
/external/strace/linux/x86_64/
Duserent.h12 XLAT(8*RCX),
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86SelectionDAGInfo.cpp130 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : in EmitTargetCodeForMemset()
149 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : in EmitTargetCodeForMemset()
220 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : in EmitTargetCodeForMemcpy()
DX86RegisterInfo.cpp673 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegister()
685 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegister()
722 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegister()
758 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegister()
794 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegister()
795 return X86::RCX; in getX86SubSuperRegister()
DX86RegisterInfo.td126 def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>;
313 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
347 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)> {
356 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
363 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX,
387 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)> {
DX86CallingConv.td148 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
203 // Do not pass the sret argument in RCX, the Win64 thiscall calling
204 // convention requires "this" to be passed in RCX.
209 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
215 [RCX , RDX , R8 , R9 ]>>,
/external/llvm/test/DebugInfo/X86/
Ddw_op_minus.ll65 ; RCX - 400
74 ; RCX is clobbered in call @Capture, but there is a spilled copy.
/external/kernel-headers/original/uapi/asm-x86/asm/
Dptrace-abi.h44 #define RCX 88 macro
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/X86/
Denhanced.txt5 # CHECK: [o:movq][w: ][1-r:%gs=r63][1-p::][1-l:8=8][p:,][w: ][0-r:%rcx=r108] <mov> 0:[RCX/108]=0 1:…
/external/valgrind/coregrind/m_sigframe/
Dsigframe-amd64-darwin.c107 SC2(__rcx,RCX); in synthesize_ucontext()
135 SC2(RCX,__rcx); in restore_from_ucontext()

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