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/external/llvm/test/CodeGen/X86/
Dvector-shuffle-sse1.ll2 ; RUN: llc < %s -mcpu=x86-64 -mattr=-sse2 | FileCheck %s --check-prefix=SSE1
7 ; SSE1-LABEL: shuffle_v4f32_0001:
8 ; SSE1: # BB#0:
9 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,1]
10 ; SSE1-NEXT: retq
15 ; SSE1-LABEL: shuffle_v4f32_0020:
16 ; SSE1: # BB#0:
17 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,2,0]
18 ; SSE1-NEXT: retq
23 ; SSE1-LABEL: shuffle_v4f32_0300:
[all …]
Dvec_fneg.ll2 …ple=i686-unknown-unknown -mattr=+sse | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE1
4 …e=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE1
55 ; X32-SSE1-LABEL: fneg_bitcast:
56 ; X32-SSE1: # BB#0:
57 ; X32-SSE1-NEXT: pushl %ebp
58 ; X32-SSE1-NEXT: movl %esp, %ebp
59 ; X32-SSE1-NEXT: andl $-16, %esp
60 ; X32-SSE1-NEXT: subl $32, %esp
61 ; X32-SSE1-NEXT: movl $-2147483648, %eax # imm = 0x80000000
62 ; X32-SSE1-NEXT: movl 12(%ebp), %ecx
[all …]
Dmemcpy-2.ll3 …llc < %s -mattr=+sse,-sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE1
28 ; SSE1-LABEL: t1:
29 ; SSE1: movaps _.str, %xmm0
30 ; SSE1: movaps %xmm0
31 ; SSE1: movb $0, 24(%esp)
32 ; SSE1: movl $0, 20(%esp)
33 ; SSE1: movl $0, 16(%esp)
68 ; SSE1-LABEL: t2:
69 ; SSE1: movaps (%ecx), %xmm0
70 ; SSE1: movaps %xmm0, (%eax)
[all …]
Dmemset-sse-stack-realignment.ll5 ; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=pentium3 | FileCheck %s -check-prefix=SSE1
21 ; SSE1-LABEL: test1:
22 ; SSE1: andl $-16
23 ; SSE1: movl %esp, %esi
24 ; SSE1: movaps
54 ; SSE1-LABEL: test2:
55 ; SSE1: andl $-16
56 ; SSE1: movl %esp, %esi
57 ; SSE1: movaps
Dsoft-fp.ll6 ; RUN: | FileCheck %s --check-prefix=SSE1 --check-prefix=CHECK
41 ; SSE1: xmm{{[0-9]+}}
54 ; SSE1: xmm{{[0-9]+}}
Dsse1.ll1 ; Tests for SSE1 and below, without SSE2+.
37 ; vselect. With SSE1 v4f32 is a legal type but v4i1 (or any vector integer type)
51 ; v4i32 isn't legal for SSE1, but this should be cmpps.
Dinline-sse.ll6 ; PR16133 - we must treat XMM registers as v4f32 as SSE1 targets don't permit other vector types.
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dmemcpy-2.ll2 …llc < %s -mattr=+sse,-sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE1
18 ; SSE1: t1:
19 ; SSE1: movaps _.str, %xmm0
20 ; SSE1: movaps %xmm0
21 ; SSE1: movb $0
22 ; SSE1: movl $0
23 ; SSE1: movl $0
54 ; SSE1: t2:
55 ; SSE1: movaps (%eax), %xmm0
56 ; SSE1: movaps %xmm0, (%eax)
[all …]
Dsse1.ll1 ; Tests for SSE1 and below, without SSE2+.
/external/skia/src/core/
DSkCpu.h15 SSE1 = 1 << 0, enumerator
62 features |= SSE1; in Supports()
91 features &= (SkCpu::SSE1 | SkCpu::SSE2 | SkCpu::SSE3 | SkCpu::SSSE3 | SkCpu::SSE41); in Supports()
93 features &= (SkCpu::SSE1 | SkCpu::SSE2); in Supports()
DSkCpu.cpp45 if (abcd[3] & (1<<25)) { features |= SkCpu:: SSE1; } in read_cpu_features()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86Subtarget.h45 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42 enumerator
173 bool hasSSE1() const { return X86SSELevel >= SSE1; } in hasSSE1()
DX86InstrFormats.td301 // SSE1 Instruction Templates:
303 // SSI - SSE1 instructions with XS prefix.
304 // PSI - SSE1 instructions with TB prefix.
305 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
306 // VSSI - SSE1 instructions with XS prefix in AVX form.
307 // VPSI - SSE1 instructions with TB prefix in AVX form.
DX86.td42 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
45 // SSE1+ processors support them.
DX86Subtarget.cpp192 if ((EDX >> 25) & 1) { X86SSELevel = SSE1; ToggleFeature(X86::FeatureSSE1); } in AutoDetectSubtargetFeatures()
DX86GenSubtargetInfo.inc177 if ((Bits & X86::FeatureSSE1) != 0 && X86SSELevel < SSE1) X86SSELevel = SSE1;
DX86InstrFPStack.td119 // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.
/external/llvm/lib/Target/X86/
DX86Subtarget.h49 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F enumerator
382 bool hasSSE1() const { return X86SSELevel >= SSE1; } in hasSSE1()
DX86InstrFormats.td515 // SSE1 Instruction Templates:
517 // SSI - SSE1 instructions with XS prefix.
518 // PSI - SSE1 instructions with PS prefix.
519 // PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix.
520 // VSSI - SSE1 instructions with XS prefix in AVX form.
521 // VPSI - SSE1 instructions with PS prefix in AVX form, packed single.
DX86.td58 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
61 // SSE1+ processors support them.
DX86InstrFPStack.td118 // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.
DX86RegisterInfo.td467 // Ensure that float types are declared first - only float is legal on SSE1.
/external/vulkan-validation-layers/libs/glm/detail/
Dintrinsic_geometric.inl63 // SSE1
/external/clang/lib/Basic/
DTargets.cpp2302 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F enumerator
3097 case SSE1: in setSSELevel()
3107 case SSE1: in setSSELevel()
3202 setSSELevel(Features, SSE1, Enabled); in setFeatureEnabledImpl()
3366 .Case("+sse", SSE1) in handleTargetFeatures()
3388 if ((FPMath == FP_SSE && SSELevel < SSE1) || in handleTargetFeatures()
3389 (FPMath == FP_387 && SSELevel >= SSE1)) { in handleTargetFeatures()
3689 case SSE1: in getTargetDefines()
3708 case SSE1: in getTargetDefines()
3778 .Case("sse", SSELevel >= SSE1) in hasFeature()
/external/valgrind/docs/internals/
D3_0_BUGSTATUS.txt426 110274 SSE1 now mandatory for x86

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