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Searched refs:hasSubClassEq (Results 1 – 25 of 29) sorted by relevance

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/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp192 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
194 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
196 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) in storeRegToStack()
198 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) in storeRegToStack()
200 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) in storeRegToStack()
202 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) in storeRegToStack()
204 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
206 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
208 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
218 else if (Mips::LO32RegClass.hasSubClassEq(RC)) in storeRegToStack()
[all …]
DMips16InstrInfo.cpp101 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) in storeRegToStack()
120 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) in loadRegFromStack()
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp708 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && in canInsertSelect()
709 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && in canInsertSelect()
710 !PPC::G8RCRegClass.hasSubClassEq(RC) && in canInsertSelect()
711 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) in canInsertSelect()
742 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) || in insertSelect()
743 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC); in insertSelect()
745 PPC::GPRCRegClass.hasSubClassEq(RC) || in insertSelect()
746 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && in insertSelect()
966 if (PPC::GPRCRegClass.hasSubClassEq(RC) || in StoreRegToStackSlot()
967 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { in StoreRegToStackSlot()
[all …]
DPPCVSXCopy.cpp59 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
DPPCVSXSwapRemoval.cpp166 return RC->hasSubClassEq(MRI->getRegClass(Reg)); in isRegInClass()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCInstrInfo.cpp337 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) { in StoreRegToStackSlot()
353 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) { in StoreRegToStackSlot()
369 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) { in StoreRegToStackSlot()
374 } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) { in StoreRegToStackSlot()
379 } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) { in StoreRegToStackSlot()
417 } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) { in StoreRegToStackSlot()
451 } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) { in StoreRegToStackSlot()
502 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) { in LoadRegFromStackSlot()
511 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) { in LoadRegFromStackSlot()
520 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) { in LoadRegFromStackSlot()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp308 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg)); in canFoldIntoCSel()
382 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) || in canInsertSelect()
383 AArch64::GPR32allRegClass.hasSubClassEq(RC)) { in canInsertSelect()
396 if (AArch64::FPR64RegClass.hasSubClassEq(RC) || in canInsertSelect()
397 AArch64::FPR32RegClass.hasSubClassEq(RC)) { in canInsertSelect()
777 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) && in UpdateOperandRegClass()
2195 if (AArch64::FPR8RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
2199 if (AArch64::FPR16RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
2203 if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
2209 } else if (AArch64::FPR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
[all …]
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetRegisterInfo.h143 return RC != this && hasSubClassEq(RC); in hasSubClass()
148 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq() function
162 return RC->hasSubClassEq(this); in hasSuperClassEq()
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinISelDAGToDAG.cpp120 return BF::AnyCCRegClass.hasSubClassEq(RC); in isCC()
124 return BF::DRegClass.hasSubClassEq(RC) || isCC(RC); in isDCC()
DBlackfinInstrInfo.cpp166 return Test.hasSubClassEq(RC); in inClass()
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h145 return RC != this && hasSubClassEq(RC); in hasSubClass()
149 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq() function
162 return RC->hasSubClassEq(this); in hasSuperClassEq()
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp418 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
421 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
456 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
459 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
/external/llvm/lib/CodeGen/GlobalISel/
DRegisterBank.cpp42 if (!RC.hasSubClassEq(&SubRC)) in verify()
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.cpp879 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
883 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
887 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
891 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
895 } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
899 } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
903 } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
908 } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
913 } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
918 } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMBaseInstrInfo.cpp721 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
725 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
733 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
741 if (ARM::QPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
757 if (ARM::QQPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
779 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
872 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
876 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
883 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
890 if (ARM::QPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
[all …]
DThumb1RegisterInfo.cpp51 if (ARM::tGPRRegClass.hasSubClassEq(RC)) in getLargestLegalSuperClass()
/external/llvm/lib/Target/ARM/
DARMBaseInstrInfo.cpp880 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
884 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
892 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
896 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
917 if (ARM::DPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
934 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
954 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
976 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1062 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1066 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
[all …]
DThumb2InstrInfo.cpp147 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
188 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
DThumbRegisterInfo.cpp49 if (ARM::tGPRRegClass.hasSubClassEq(RC)) in getLargestLegalSuperClass()
/external/llvm/lib/Target/Lanai/
DLanaiInstrInfo.cpp60 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) { in storeRegToStackSlot()
80 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) { in loadRegFromStackSlot()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrInfo.cpp2255 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"); in getLoadStoreRegOpcode()
2259 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
2263 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); in getLoadStoreRegOpcode()
2266 if (X86::GR32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
2268 if (X86::FR32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
2272 if (X86::RFP32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
2276 if (X86::GR64RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
2278 if (X86::FR64RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
2282 if (X86::VR64RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
2284 if (X86::RFP64RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
[all …]
/external/llvm/lib/Target/X86/
DX86InstrInfo.cpp4298 if (X86::GR16RegClass.hasSubClassEq(RC) || in canInsertSelect()
4299 X86::GR32RegClass.hasSubClassEq(RC) || in canInsertSelect()
4300 X86::GR64RegClass.hasSubClassEq(RC)) { in canInsertSelect()
4375 return X86::VK16RegClass.hasSubClassEq(RC); in isMaskRegClass()
4615 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
4617 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
4619 if (X86::VR512RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
4628 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"); in getLoadStoreRegOpcode()
4632 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
4636 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); in getLoadStoreRegOpcode()
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DTargetInstrInfoImpl.cpp253 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg))) in canFoldCopy()
/external/llvm/lib/CodeGen/
DMachineFunction.cpp525 RC->hasSubClassEq(VRegRC))) && in addLiveIn()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp509 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) in EmitSubregNode()

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