| /external/llvm/lib/Target/ARM/ |
| D | ARMSubtarget.h | 396 bool hasV6Ops() const { return HasV6Ops; } in hasV6Ops() function
444 return HasDataBarrier || (hasV6Ops() && !isThumb()); in hasAnyDataBarrier()
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| D | Thumb1InstrInfo.cpp | 51 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg) in copyPhysReg()
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| D | ARMSubtarget.cpp | 328 if (!hasV6Ops()) in useFastISel()
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| D | ARMISelDAGToDAG.cpp | 2912 Subtarget->hasV6Ops() ? ARM::UMULL : ARM::UMULLv5, dl, in Select()
2931 Subtarget->hasV6Ops() ? ARM::SMULL : ARM::SMULLv5, dl, in Select()
2948 if (Subtarget->hasV6Ops() && N->getOperand(2).getOpcode() == ARMISD::ADDC && in Select()
2990 Subtarget->hasV6Ops() ? ARM::UMLAL : ARM::UMLALv5, dl, in Select()
3009 Subtarget->hasV6Ops() ? ARM::SMLAL : ARM::SMLALv5, dl, in Select()
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| D | ARMFastISel.cpp | 2666 bool hasV6Ops = Subtarget->hasV6Ops(); in ARMEmitIntExt() local
2670 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt]; in ARMEmitIntExt()
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| D | ARMLoadStoreOptimizer.cpp | 702 !STI->hasV6Ops()) { in CreateLoadStoreMulti()
2095 unsigned ReqAlign = STI->hasV6Ops() in CanFormLdStDWord()
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| D | ARMISelLowering.cpp | 732 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops() in ARMTargetLowering()
772 if (!Subtarget->hasV6Ops()) in ARMTargetLowering()
891 if (!Subtarget->hasV6Ops()) { in ARMTargetLowering()
1033 if (Subtarget->hasV6Ops()) in ARMTargetLowering()
1283 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4); in shouldAlignPointerArgs()
3007 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && in LowerATOMIC_FENCE()
8957 if (!Subtarget->hasV6Ops()) in AddCombineTo64bitUMAAL()
10700 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) { in PerformShiftCombine()
11680 if (!Subtarget->hasV6Ops()) in ExpandInlineAsm()
12334 if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) { in makeDMB()
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| D | ARMAsmPrinter.cpp | 605 else if (Subtarget->hasV6Ops()) in getArchForCPU()
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| D | ARMInstrInfo.td | 194 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
196 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMSubtarget.h | 191 bool hasV6Ops() const { return HasV6Ops; } in hasV6Ops() function
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| D | ARMSubtarget.cpp | 126 if (!StrictAlign && hasV6Ops() && isTargetDarwin()) in ARMSubtarget()
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| D | ARMFastISel.cpp | 2027 if (!Subtarget->hasV6Ops()) return false; in SelectIntCast()
2034 if (!Subtarget->hasV6Ops()) return false; in SelectIntCast()
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| D | ARMISelLowering.cpp | 554 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops() in ARMTargetLowering()
580 if (!Subtarget->hasV6Ops()) in ARMTargetLowering()
619 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) { in ARMTargetLowering()
661 if (!Subtarget->hasV6Ops()) { in ARMTargetLowering()
2281 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && in LowerMEMBARRIER()
2311 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && in LowerATOMIC_FENCE()
8420 if (!Subtarget->hasV6Ops()) in ExpandInlineAsm()
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| D | ARMLoadStoreOptimizer.cpp | 1539 unsigned ReqAlign = STI->hasV6Ops() in CanFormLdStDWord()
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| D | ARMISelDAGToDAG.cpp | 2571 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ? in Select()
2587 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ? in Select()
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| D | ARMInstrInfo.td | 174 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
176 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 114 bool hasV6Ops() const { in hasV6Ops() function in __anon10a3738d0111::ARMAsmParser
4392 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && in checkTargetMatchPredicate()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 263 bool hasV6Ops() const { in hasV6Ops() function in __anon58d02de10111::ARMAsmParser
8783 else if (Opc == ARM::tMOVr && !hasV6Ops() && in checkTargetMatchPredicate()
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