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/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td1792 class LoadParamMemInst<NVPTXRegClass regclass, string opstr> :
1793 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1798 class LoadParamV2MemInst<NVPTXRegClass regclass, string opstr> :
1799 NVPTXInst<(outs regclass:$dst, regclass:$dst2), (ins i32imm:$b),
1803 class LoadParamV4MemInst<NVPTXRegClass regclass, string opstr> :
1804 NVPTXInst<(outs regclass:$dst, regclass:$dst2, regclass:$dst3,
1805 regclass:$dst4),
1812 class LoadParamRegInst<NVPTXRegClass regclass, string opstr> :
1813 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1815 [(set regclass:$dst, (LoadParam (i32 0), (i32 imm:$b)))]>;
[all …]
DNVPTXVector.td239 class VecBinaryOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass,
241 NVPTXVecInst<(outs regclass:$dst), (ins regclass:$a, regclass:$b),
243 [(set regclass:$dst, (OpNode regclass:$a, regclass:$b))],
253 class VecUnaryOp<BinOpAsmString asmstr, PatFrag OpNode, NVPTXRegClass regclass,
255 NVPTXVecInst<(outs regclass:$dst), (ins regclass:$a),
257 [(set regclass:$dst, (OpNode regclass:$a))], sInst>;
493 multiclass VMADV2Only<string asmstr, NVPTXRegClass regclass, NVPTXInst sop=NOP,
495 def V2 : NVPTXVecInst<(outs regclass:$dst),
496 (ins regclass:$a, regclass:$b, regclass:$c),
498 [(set regclass:$dst, (add
[all …]
DNVPTXIntrinsics.td69 multiclass SHFL<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
75 (outs regclass:$dst),
76 (ins regclass:$src, Int32Regs:$offset, Int32Regs:$mask),
78 [(set regclass:$dst, (IntOp regclass:$src, Int32Regs:$offset, Int32Regs:$mask))]>;
81 (outs regclass:$dst),
82 (ins regclass:$src, i32imm:$offset, Int32Regs:$mask),
84 [(set regclass:$dst, (IntOp regclass:$src, imm:$offset, Int32Regs:$mask))]>;
87 (outs regclass:$dst),
88 (ins regclass:$src, Int32Regs:$offset, i32imm:$mask),
90 [(set regclass:$dst, (IntOp regclass:$src, Int32Regs:$offset, imm:$mask))]>;
[all …]
/external/libunwind_llvm/src/
DUnwind-EHABI.cpp754 _Unwind_VRS_Set(_Unwind_Context *context, _Unwind_VRS_RegClass regclass, in _Unwind_VRS_Set() argument
759 static_cast<void *>(context), regclass, regno, in _Unwind_VRS_Set()
763 switch (regclass) { in _Unwind_VRS_Set()
813 _Unwind_VRS_RegClass regclass, uint32_t regno, in _Unwind_VRS_Get_Internal() argument
817 switch (regclass) { in _Unwind_VRS_Get_Internal()
866 _Unwind_VRS_Get(_Unwind_Context *context, _Unwind_VRS_RegClass regclass, in _Unwind_VRS_Get() argument
870 _Unwind_VRS_Get_Internal(context, regclass, regno, representation, in _Unwind_VRS_Get()
874 static_cast<void *>(context), regclass, regno, in _Unwind_VRS_Get()
881 _Unwind_VRS_Pop(_Unwind_Context *context, _Unwind_VRS_RegClass regclass, in _Unwind_VRS_Pop() argument
886 static_cast<void *>(context), regclass, discriminator, in _Unwind_VRS_Pop()
[all …]
/external/libunwind_llvm/include/
Dunwind.h196 _Unwind_VRS_Get(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
201 _Unwind_VRS_Set(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
206 _Unwind_VRS_Pop(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
/external/llvm/test/CodeGen/PowerPC/
Dvariable_elem_vec_extracts.ll100 ; FIXME: the instruction below is a redundant regclass copy, to be removed
106 ; FIXME: the instruction below is a redundant regclass copy, to be removed
112 ; FIXME: the instruction below is a redundant regclass copy, to be removed
/external/llvm/test/CodeGen/X86/
Dcoalescer-subreg.ll2 ; This used to crash when coalescing a regclass like GR16 which did not support
Dh-registers-0.ll14 ; See FIXME: on regclass GR8.
/external/swiftshader/third_party/LLVM/test/CodeGen/Blackfin/
Dinline-asm.ll24 ; Target "z" for P0, P1, P2. This is not a real regclass
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dh-registers-0.ll13 ; See FIXME: on regclass GR8.
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTarget.td439 /// type that it doesn't know, and resolves the actual regclass to use by using
522 class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> {
524 RegisterClass RegClass = regclass;
657 let InOperandList = (ins unknown:$src, i32imm:$regclass);
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvldlane.ll491 ; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because
492 ; we don't currently have a QQQQ_VFP2 super-regclass. (The "0" for the low
/external/llvm/include/llvm/Target/
DTargetOpcodes.def81 // pair. Once it has been lowered to a MachineInstr, the regclass operand
DTarget.td553 /// type that it doesn't know, and resolves the actual regclass to use by using
664 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
667 RegisterClass RegClass = regclass;
849 let InOperandList = (ins unknown:$src, i32imm:$regclass);
/external/llvm/test/CodeGen/ARM/
Dvldlane.ll503 ; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because
504 ; we don't currently have a QQQQ_VFP2 super-regclass. (The "0" for the low
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrArithmetic.td503 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
517 RegisterClass RegClass = regclass;
610 // just a regclass (no eflags) as a result.
627 // both a regclass and EFLAGS as a result.
635 // both a regclass and EFLAGS as a result, and has EFLAGS as input.
DX86RegisterInfo.td166 // The sub_ss and sub_sd subregs are the same registers with another regclass.
/external/llvm/lib/Target/X86/
DX86InstrArithmetic.td550 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
565 RegisterClass RegClass = regclass;
672 // both a regclass and EFLAGS as a result.
681 // both a regclass and EFLAGS as a result, and has EFLAGS as input.
/external/llvm/test/CodeGen/AMDGPU/
Dsgpr-copy.ll222 ; registers were being identified as an SGPR regclass which was causing
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td204 // Condition code regclass.
DAArch64InstrFormats.td584 class arith_shifted_reg<ValueType Ty, RegisterClass regclass, int width>
588 let MIOperandInfo = (ops regclass, !cast<Operand>("arith_shift" # width));
606 class logical_shifted_reg<ValueType Ty, RegisterClass regclass, Operand shiftop>
610 let MIOperandInfo = (ops regclass, shiftop);
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrInfo.td1891 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1934 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
DARMInstrThumb2.td1214 // can be SP. We need another regclass (similar to rGPR) to represent
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td1325 // can be SP. We need another regclass (similar to rGPR) to represent
DARMInstrInfo.td2251 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.

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