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Searched refs:vcc (Results 1 – 25 of 102) sorted by relevance

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/external/mesa3d/src/gallium/drivers/ilo/shader/
Dilo_shader_vs.c59 vs_lower_opcode_tgsi_in(struct vs_compile_context *vcc, in vs_lower_opcode_tgsi_in() argument
62 struct toy_compiler *tc = &vcc->tc; in vs_lower_opcode_tgsi_in()
67 slot = toy_tgsi_find_input(&vcc->tgsi, idx); in vs_lower_opcode_tgsi_in()
69 const int first_in_grf = vcc->first_vue_grf + in vs_lower_opcode_tgsi_in()
70 (vcc->shader->in.count - vcc->tgsi.num_inputs); in vs_lower_opcode_tgsi_in()
71 const int grf = first_in_grf + vcc->tgsi.inputs[slot].semantic_index; in vs_lower_opcode_tgsi_in()
83 vs_lower_opcode_tgsi_const_pcb(struct vs_compile_context *vcc, in vs_lower_opcode_tgsi_const_pcb() argument
88 const int grf = vcc->first_const_grf + i / 2; in vs_lower_opcode_tgsi_const_pcb()
92 if (!vcc->variant->use_pcb || dim != 0 || idx.file != TOY_FILE_IMM || in vs_lower_opcode_tgsi_const_pcb()
93 grf >= vcc->first_ucp_grf) in vs_lower_opcode_tgsi_const_pcb()
[all …]
/external/llvm/test/MC/AMDGPU/
Dvopc.s10 v_cmp_lt_f32 vcc, s2, v4
15 v_cmp_lt_f32 vcc, 0, v4
20 v_cmp_lt_f32 vcc, 10.0, v4
25 v_cmp_lt_f32 vcc, v255, v255
30 v_cmp_lt_f32_e32 vcc, v2, v4
39 v_cmp_f_f32 vcc, v2, v4
43 v_cmp_lt_f32 vcc, v2, v4
50 v_cmp_f_f64 vcc, v[2:3], v[4:5]
57 v_cmp_f_i32 vcc, v2, v4
63 v_cmp_f_i64 vcc, v[2:3], v[4:5]
Dvop2.s99 v_add_i32 v0, vcc, 0.5, v0
103 v_add_i32 v0, vcc, 3.125, v0
110 v_cndmask_b32 v1, v2, v3, vcc
113 v_cndmask_b32_e32 v1, v2, v3, vcc
267 v_add_i32 v1, vcc, v2, v3
279 v_add_i32_e64 v1, vcc, v2, v3
283 v_add_u32 v1, vcc, v2, v3
291 v_sub_i32 v1, vcc, v2, v3
299 v_sub_u32 v1, vcc, v2, v3
307 v_subrev_i32 v1, vcc, v2, v3
[all …]
Dvop3.s19 v_cmp_lt_f32_e64 vcc, v4, v6
209 v_cndmask_b32_e64 v1, v3, v5, vcc
325 v_div_scale_f64 v[24:25], vcc, v[22:23], v[22:23], v[20:21]
333 v_div_scale_f32 v24, vcc, v22, v22, v20
337 v_div_scale_f32 v24, vcc, s[10:11], v22, v20
345 v_div_scale_f32 v24, vcc, v22, 1.0, v22
349 v_div_scale_f32 v24, vcc, v22, v22, -2.0
353 v_div_scale_f32 v24, vcc, v22, v22, 0xc0000000
Dvop2-err.s44 v_addc_u32_e32 v1, vcc, v2, v3, s[2:3]
50 v_addc_u32_e32 v1, vcc, v2, v3, -1
53 v_addc_u32_e32 v1, vcc, v2, v3, 123
56 v_addc_u32_e32 v1, vcc, v2, v3, s0
Dvop_sdwa.s117 v_cmp_class_f32 vcc, -v1, sext(v2) src0_sel:BYTE_2 src1_sel:WORD_0
509 v_cmp_eq_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
513 v_cmp_nle_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
517 v_cmpx_gt_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
521 v_cmpx_nlt_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
525 v_cmp_lt_i32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
529 v_cmp_t_i32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
533 v_cmpx_eq_i32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
537 v_cmpx_ne_i32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
541 v_cmp_f_u32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
[all …]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dvopc_vi.txt3 # VI: v_cmp_lt_f32_e32 vcc, s2, v4 ; encoding: [0x02,0x08,0x82,0x7c]
6 # VI: v_cmp_lt_f32_e32 vcc, 0, v4 ; encoding: [0x80,0x08,0x82,0x7c]
9 # VI: v_cmp_lt_f32_e32 vcc, 0x41200000, v4 ; encoding: [0xff,0x08,0x82,0x7c,0x00,0x00,0x20,0x41]
12 # VI: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x83,0x7c]
15 # VI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c]
18 # VI: v_cmp_f_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x80,0x7c]
21 # VI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c]
24 # VI: v_cmp_f_f64_e32 vcc, v[2:3], v[4:5] ; encoding: [0x02,0x09,0xc0,0x7c]
27 # VI: v_cmp_f_i32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x80,0x7d]
30 # VI: v_cmp_f_i64_e32 vcc, v[2:3], v[4:5] ; encoding: [0x02,0x09,0xc0,0x7d]
Dvop2_vi.txt3 # VI: v_cndmask_b32_e32 v1, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x00]
96 # VI: v_add_i32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x32]
105 # VI: v_add_i32_e64 v1, vcc, v2, v3 ; encoding: [0x01,0x6a,0x19,0xd1,0x02,0x07,0x02,0x00]
108 # VI: v_add_i32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x32]
114 # VI: v_sub_i32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x34]
120 # VI: v_sub_i32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x34]
126 # VI: v_subrev_i32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x36]
132 # VI: v_subrev_i32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x36]
138 # VI: v_addc_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x38]
141 # VI: v_addc_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x38]
[all …]
/external/llvm/test/Object/AMDGPU/
Dobjdump.s14 v_add_i32_e32 v1, vcc, s0, v1
16 v_cmp_ge_i32_e32 vcc, s0, v0
17 s_and_saveexec_b64 s[0:1], vcc
30 s_and_saveexec_b64 s[0:1], vcc
36 v_add_i32_e32 v10, vcc, s8, v10
38 v_addc_u32_e32 v11, vcc, v6, v11, vcc
/external/llvm/test/MC/AMDGPU/regression/
Dbug28413.s6 v_cmp_eq_i32 vcc, 0.5, v0
14 v_cmp_eq_i32 vcc, 3.125, v0
18 v_cmpx_eq_u32 vcc, 3.125, v0
28 v_add_i32 v0, vcc, 0.5, v0
32 v_add_i32 v0, vcc, 3.125, v0
/external/llvm/test/CodeGen/AMDGPU/
Dsmrd-vccz-bug.ll8 ; GCN: s_and_b64 vcc, exec, [[MASK]]
10 ; VCCZ-BUG: s_mov_b64 vcc, vcc
11 ; NOVCCZ-BUG-NOT: s_mov_b64 vcc, vcc
31 ; GCN: v_cmp_neq_f32_e32 vcc, 0, v{{[0-9]+}}
32 ; GCN: s_and_b64 vcc, exec, vcc
Dsetcc-opt.ll7 ; GCN: v_cmp_ne_i32_e32 vcc,
8 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
24 ; GCN: v_cmp_ne_i32_e32 vcc,
25 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
41 ; GCN: v_cmp_eq_i32_e32 vcc,
42 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
55 ; GCN: v_cmp_eq_i32_e32 vcc,
56 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
69 ; GCN: v_cmp_ne_i32_e32 vcc,
70 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
[all …]
Dskip-if-dead.ll37 ; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0
48 ; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0
50 ; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0
61 ; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0
63 ; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v1
74 ; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0
77 ; CHECK: v_cmpx_le_f32_e32 vcc, 0, v7
106 ; CHECK: v_cmpx_le_f32_e32 vcc, 0, v7
156 ; CHECK: v_cmpx_le_f32_e32 vcc, 0, v7
202 ; CHECK: v_cmp_eq_i32_e32 vcc, 0, v0
[all …]
Dcommute-compares.ll10 ; GCN: v_cmp_eq_i32_e32 vcc, 64, v{{[0-9]+}}
23 ; GCN: v_cmp_ne_i32_e32 vcc, 64, v{{[0-9]+}}
38 ; GCN: v_cmp_ne_i32_e32 vcc, [[K]], v{{[0-9]+}}
51 ; GCN: v_cmp_lt_u32_e32 vcc, 64, v{{[0-9]+}}
64 ; GCN: v_cmp_lt_u32_e32 vcc, 63, v{{[0-9]+}}
77 ; GCN: v_cmp_gt_u32_e32 vcc, 64, v{{[0-9]+}}
90 ; GCN: v_cmp_gt_u32_e32 vcc, 64, v{{[0-9]+}}
106 ; GCN: v_cmp_gt_u32_e32 vcc, [[K]], v{{[0-9]+}}
119 ; GCN: v_cmp_lt_i32_e32 vcc, -1, v{{[0-9]+}}
132 ; GCN: v_cmp_lt_i32_e32 vcc, -3, v{{[0-9]+}}
[all …]
Dsetcc64.ll61 ; SI: v_cmp_lg_f64_e32 vcc
62 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
82 ; SI: v_cmp_nlg_f64_e32 vcc
83 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
94 ; SI: v_cmp_nle_f64_e32 vcc
95 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
105 ; SI: v_cmp_nlt_f64_e32 vcc
106 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
116 ; SI: v_cmp_nge_f64_e32 vcc
117 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
[all …]
Dvalu-i1.ll46 ; SI: v_cmp_ne_i32_e32 vcc, 0, v{{[0-9]+}}
47 ; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
72 ; SI: v_cmp_ne_i32_e32 vcc, 0, v{{[0-9]+}}
73 ; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
82 ; SI-DAG: v_cmp_eq_i32_e32 vcc,
83 ; SI-DAG: s_and_b64 vcc, exec, vcc
115 ; SI: v_cmp_lt_i32_e32 vcc
116 ; SI: s_and_saveexec_b64 [[OUTER_CMP_SREG:s\[[0-9]+:[0-9]+\]]], vcc
130 ; SI-DAG: v_cmp_ne_i32_e32 [[NEG1_CHECK_1:vcc]], -1, [[B]]
138 ; SI: v_cmp_ge_i64_e32 [[CMP:s\[[0-9]+:[0-9]+\]|vcc]]
Duniform-cfg.ll34 ; SI-DAG: v_cmp_eq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}}
35 ; SI-DAG: s_and_b64 vcc, exec, [[COND]]
91 ; SI-DAG: v_cmp_neq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}}
92 ; SI-DAG: s_and_b64 vcc, exec, [[COND]]
122 ; SI: v_cmp_ne_i32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 5, [[CMP]]
123 ; SI: s_and_b64 vcc, exec, [[COND]]
147 ; SI: v_cmp_gt_u32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 6, [[CMP]]
148 ; SI: s_and_b64 vcc, exec, [[COND]]
257 ; SI: s_and_b64 vcc, exec, [[MASK]]
286 ; SI: v_add_i32_e32 [[I:v[0-9]+]], vcc, -1, v{{[0-9]+}}
[all …]
Dfcmp64.ll5 ; CHECK: v_cmp_nge_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
17 ; CHECK: v_cmp_ngt_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
29 ; CHECK: v_cmp_nle_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
41 ; CHECK: v_cmp_nlt_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
53 ; CHECK: v_cmp_neq_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
65 ; CHECK: v_cmp_nlg_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
Dsplit-scalar-i64-add.ll7 ; set in vcc, which is undefined since the low scalar half add sets
11 ; SI: v_add_i32_e32 v{{[0-9]+}}, vcc, 0x18f, v{{[0-9]+}}
12 ; SI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
62 ; SI: v_add_i32_e32 {{v[0-9]+}}, vcc, {{s[0-9]+}}, {{v[0-9]+}}
63 ; SI: v_addc_u32_e32 {{v[0-9]+}}, vcc, {{v[0-9]+}}, {{v[0-9]+}}, vcc
Dcndmask-no-def-vcc.ll8 ; GCN: v_cmp_eq_i32_e64 vcc, 0, s{{[0-9]+}}
9 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc
32 ; implicit vcc use to avoid verifier errors.
35 ; GCN-NOT: vcc
36 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc
Dllvm.amdgcn.class.ll13 ; SI: v_cmp_class_f32_e32 vcc, [[SA]], [[VB]]
14 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
103 ; SI: v_cmp_class_f32_e32 vcc, [[SA]], [[MASK]]
104 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
117 ; SI: v_cmp_class_f32_e32 vcc, [[SA]], [[MASK]]
118 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
131 ; SI: v_cmp_class_f32_e32 vcc, [[VA]], [[MASK]]
132 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
149 ; SI: v_cmp_class_f32_e32 vcc, 1.0, [[VB]]
150 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
[all …]
Dds-sub-offset.ll9 ; GCN: v_sub_i32_e32 [[BASEPTR:v[0-9]+]], vcc, 0, [[SHL]]
24 ; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
39 ; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x10000, [[SCALED]]
54 ; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
76 ; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
96 ; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
110 ; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x3fc, [[SCALED]]
Dsub.ll10 ; SI: v_subrev_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
25 ; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
26 ; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
43 ; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
44 ; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
45 ; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
46 ; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
Dllvm.amdgcn.div.fmas.ll80 ; SI: v_cmp_eq_i32_e64 vcc, 0, s{{[0-9]+}}
90 ; SI: s_mov_b64 vcc, 0
99 ; SI: s_mov_b64 vcc, -1
112 ; SI-DAG: v_cmp_eq_i32_e32 [[CMP0:vcc]], 0, v{{[0-9]+}}
114 ; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]]
138 ; SI: v_cmp_eq_i32_e32 vcc, 0, v{{[0-9]+}}
139 ; SI: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], vcc
143 ; SI: v_cmp_ne_i32_e32 vcc, 0, [[LOAD]]
144 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
149 ; SI: v_cmp_ne_i32_e32 vcc, 0, v{{[0-9]+}}
Dadd.ll8 ;SI: v_add_i32_e32 [[REG:v[0-9]+]], vcc, {{v[0-9]+, v[0-9]+}}
24 ;SI: v_add_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
25 ;SI: v_add_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
42 ;SI: v_add_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
43 ;SI: v_add_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
44 ;SI: v_add_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
45 ;SI: v_add_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}

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