/external/llvm/test/MC/ARM/ |
D | neon-vld-encoding.s | 157 vld3.8 {d16, d17, d18}, [r1] 158 vld3.16 {d6, d7, d8}, [r2] 159 vld3.32 {d1, d2, d3}, [r3] 160 vld3.8 {d16, d18, d20}, [r0:64] 161 vld3.u16 {d27, d29, d31}, [r4] 162 vld3.i32 {d6, d8, d10}, [r5] 164 vld3.i8 {d12, d13, d14}, [r6], r1 165 vld3.i16 {d11, d12, d13}, [r7], r2 166 vld3.u32 {d2, d3, d4}, [r8], r3 167 vld3.8 {d4, d6, d8}, [r9], r4 [all …]
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D | neont2-vld-encoding.s | 35 @ CHECK: vld3.8 {d16, d17, d18}, [r0:64] @ encoding: [0x60,0xf9,0x1f,0x04] 36 vld3.8 {d16, d17, d18}, [r0:64] 37 @ CHECK: vld3.16 {d16, d17, d18}, [r0] @ encoding: [0x60,0xf9,0x4f,0x04] 38 vld3.16 {d16, d17, d18}, [r0] 39 @ CHECK: vld3.32 {d16, d17, d18}, [r0] @ encoding: [0x60,0xf9,0x8f,0x04] 40 vld3.32 {d16, d17, d18}, [r0] 41 @ CHECK: vld3.8 {d16, d18, d20}, [r0:64]! @ encoding: [0x60,0xf9,0x1d,0x05] 42 vld3.8 {d16, d18, d20}, [r0:64]! 43 @ CHECK: vld3.8 {d17, d19, d21}, [r0:64]! @ encoding: [0x60,0xf9,0x1d,0x15] 44 vld3.8 {d17, d19, d21}, [r0:64]! [all …]
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D | neon-vld-vst-align.s | 2912 vld3.8 {d0, d1, d2}, [r4] 2913 vld3.8 {d0, d1, d2}, [r4:16] 2914 vld3.8 {d0, d1, d2}, [r4:32] 2915 vld3.8 {d0, d1, d2}, [r4:64] 2916 vld3.8 {d0, d1, d2}, [r4:128] 2917 vld3.8 {d0, d1, d2}, [r4:256] 2919 @ CHECK: vld3.8 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x0f,0x04] 2921 @ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:16] 2924 @ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:32] 2926 @ CHECK: vld3.8 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x04] [all …]
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/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
D | neont2-vld-encoding.s | 36 @ CHECK: vld3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x60,0xf9] 37 vld3.8 {d16, d17, d18}, [r0, :64] 38 @ CHECK: vld3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x60,0xf9] 39 vld3.16 {d16, d17, d18}, [r0] 40 @ CHECK: vld3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x60,0xf9] 41 vld3.32 {d16, d17, d18}, [r0] 42 @ CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x60,0xf9] 43 vld3.8 {d16, d18, d20}, [r0, :64]! 44 @ CHECK: vld3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x60,0xf9] 45 vld3.8 {d17, d19, d21}, [r0, :64]! [all …]
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D | neon-vld-encoding.s | 38 vld3.8 {d16, d17, d18}, [r0, :64] 39 vld3.16 {d16, d17, d18}, [r0] 40 vld3.32 {d16, d17, d18}, [r0] 41 vld3.8 {d16, d18, d20}, [r0, :64]! 42 vld3.8 {d17, d19, d21}, [r0, :64]! 43 vld3.16 {d16, d18, d20}, [r0]! 44 vld3.16 {d17, d19, d21}, [r0]! 45 vld3.32 {d16, d18, d20}, [r0]! 46 vld3.32 {d17, d19, d21}, [r0]! 48 @ CHECK: vld3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x60,0xf4] [all …]
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/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
D | vld3.ll | 18 ;CHECK: vld3.8 {d16, d17, d18}, [r0, :64] 19 %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 32) 28 ;CHECK: vld3.16 30 %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1) 40 ;CHECK: vld3.16 {d16, d17, d18}, [{{r[0-9]+}}], {{r[0-9]+}} 43 %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1) 54 ;CHECK: vld3.32 56 %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8* %tmp0, i32 1) 65 ;CHECK: vld3.32 67 %tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32(i8* %tmp0, i32 1) [all …]
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D | 2010-05-20-NEONSpillCrash.ll | 4 ; the @llvm.arm.neon.vld3.v8i8 defined three parts of a register. 8 declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8*, i32) nounwind readonly 13 …%tmp1b = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A2, i32 1) ; <%struct.__neon… 16 …%tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A4, i32 1) ; <%struct.__neon… 19 …%tmp1e = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A5, i32 1) ; <%struct.__neon… 21 …%tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A6, i32 1) ; <%struct.__neon… 23 …%tmp1g = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A7, i32 1) ; <%struct.__neon… 26 …%tmp1h = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A8, i32 1) ; <%struct.__neon…
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D | vldlane.ll | 211 ;CHECK: vld3.8 225 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}] 239 ;CHECK: vld3.32 253 ;CHECK: vld3.32 268 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}] 283 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}], {{r[0-9]+}} 300 ;CHECK: vld3.32 314 ;CHECK: vld3.32 496 ;CHECK: vld3.16
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D | reg_sequence.ll | 77 ; CHECK: vld3.8 82 …%tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 1) ; <%struct.__neon_i… 310 …%tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A4, i32 1) ; <%struct.__neon… 312 …%tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A6, i32 1) ; <%struct.__neon… 338 declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8*, i32) nounwind readonly
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D | vlddup.ll | 131 ;CHECK: vld3.8 {d16[], d17[], d18[]}, [r2], r1 150 ;CHECK: vld3.16 {d16[], d17[], d18[]}, [r0]
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/external/llvm/test/CodeGen/ARM/ |
D | vld3.ll | 18 ;CHECK: vld3.8 {d16, d17, d18}, [r0:64] 19 %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A, i32 32) 28 ;CHECK: vld3.16 30 %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16.p0i8(i8* %tmp0, i32 1) 40 ;CHECK: vld3.16 {d16, d17, d18}, [{{r[0-9]+}}], {{r[0-9]+}} 43 %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16.p0i8(i8* %tmp0, i32 1) 54 ;CHECK: vld3.32 56 %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32.p0i8(i8* %tmp0, i32 1) 65 ;CHECK: vld3.32 67 %tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32.p0i8(i8* %tmp0, i32 1) [all …]
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D | 2010-05-20-NEONSpillCrash.ll | 4 ; the @llvm.arm.neon.vld3.v8i8.p0i8 defined three parts of a register. 8 declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8*, i32) nounwind readonly 13 …%tmp1b = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A2, i32 1) ; <%struct._… 16 …%tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A4, i32 1) ; <%struct._… 19 …%tmp1e = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A5, i32 1) ; <%struct._… 21 …%tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A6, i32 1) ; <%struct._… 23 …%tmp1g = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A7, i32 1) ; <%struct._… 26 …%tmp1h = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A8, i32 1) ; <%struct._…
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D | 2012-08-27-CopyPhysRegCrash.ll | 8 declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8*, i32) nounwind reado… 22 %7 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* null, i32 1) 25 %10 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %9, i32 1) 27 %12 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %6, i32 1) 31 %16 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %15, i32 1)
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D | arm-interleaved-accesses.ll | 17 ; NEON: vld3.32 {d16, d17, d18}, [r0] 19 ; NONEON-NOT: vld3 96 ; NEON: vld3.32 {d16, d17, d18}, [r0] 98 ; NONEON-NOT: vld3 177 ; NEON: vld3.32 {d16, d18, d20}, [r0]! 178 ; NEON: vld3.32 {d17, d19, d21}, [r0] 180 ; NONEON-NOT: vld3 246 ; NEON: vld3.32 248 ; NONEON-NOT: vld3
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D | vld-vst-upgrade.ll | 28 ; CHECK: vld3.32 {d16, d17, d18}, [r1] 30 %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8* %ptr, i32 1) 34 declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8*, i32) nounwind readonly 57 ; CHECK: vld3.32 {d16[1], d17[1], d18[1]}, [r1]
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D | vldlane.ll | 223 ;CHECK: vld3.8 237 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}] 251 ;CHECK: vld3.32 265 ;CHECK: vld3.32 280 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}] 295 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}], {{r[0-9]+}} 312 ;CHECK: vld3.32 326 ;CHECK: vld3.32 508 ;CHECK: vld3.16
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D | reg_sequence.ll | 79 ; CHECK: vld3.8 84 …%tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A, i32 1) ; <%struct.__n… 310 …%tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A4, i32 1) ; <%struct._… 312 …%tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A6, i32 1) ; <%struct._… 338 declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8*, i32) nounwind readonly
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/external/llvm/test/Transforms/EarlyCSE/AArch64/ |
D | intrinsics.ll | 168 %vld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i8(i8* %5) 169 %vld3.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 0 170 %vld3.fca.2.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 2 171 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld3.fca.0.extract, <4 x i32> %vld3.fca.2.extract) 205 %vld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i8(i8* %5) 206 %vld3.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 0 207 %vld3.fca.1.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 1 208 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld3.fca.0.extract, <4 x i32> %vld3.fca.0.extract)
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/external/llvm/test/MC/Disassembler/ARM/ |
D | neont2.txt | 1412 # CHECK: vld3.8 {d16, d17, d18}, [r0:64] 1414 # CHECK: vld3.16 {d16, d17, d18}, [r0] 1416 # CHECK: vld3.32 {d16, d17, d18}, [r0] 1418 # CHECK: vld3.8 {d16, d18, d20}, [r0:64]! 1420 # CHECK: vld3.8 {d17, d19, d21}, [r0:64]! 1422 # CHECK: vld3.16 {d16, d18, d20}, [r0]! 1424 # CHECK: vld3.16 {d17, d19, d21}, [r0]! 1426 # CHECK: vld3.32 {d16, d18, d20}, [r0]! 1428 # CHECK: vld3.32 {d17, d19, d21}, [r0]! 1468 # CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0] [all …]
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D | neon.txt | 1671 # CHECK: vld3.8 {d16, d17, d18}, [r0:64] 1673 # CHECK: vld3.16 {d16, d17, d18}, [r0] 1675 # CHECK: vld3.32 {d16, d17, d18}, [r0] 1677 # CHECK: vld3.8 {d16, d18, d20}, [r0:64]! 1679 # CHECK: vld3.8 {d17, d19, d21}, [r0:64]! 1681 # CHECK: vld3.16 {d16, d18, d20}, [r0]! 1683 # CHECK: vld3.16 {d17, d19, d21}, [r0]! 1685 # CHECK: vld3.32 {d16, d18, d20}, [r0]! 1687 # CHECK: vld3.32 {d17, d19, d21}, [r0]! 1727 # CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0] [all …]
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-neon-vector-list-spill.ll | 93 …%vld3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3.v4f32.p0f32(flo… 102 %vld3.extract = extractvalue { <4 x float>, <4 x float>, <4 x float> } %vld3, 0 103 %res = extractelement <4 x float> %vld3.extract, i32 1
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/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
D | neont2.txt | 1412 # CHECK: vld3.8 {d16, d17, d18}, [r0, :64] 1414 # CHECK: vld3.16 {d16, d17, d18}, [r0] 1416 # CHECK: vld3.32 {d16, d17, d18}, [r0] 1418 # CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! 1420 # CHECK: vld3.8 {d17, d19, d21}, [r0, :64]! 1422 # CHECK: vld3.16 {d16, d18, d20}, [r0]! 1424 # CHECK: vld3.16 {d17, d19, d21}, [r0]! 1426 # CHECK: vld3.32 {d16, d18, d20}, [r0]! 1428 # CHECK: vld3.32 {d17, d19, d21}, [r0]! 1468 # CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0] [all …]
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D | neon.txt | 1671 # CHECK: vld3.8 {d16, d17, d18}, [r0, :64] 1673 # CHECK: vld3.16 {d16, d17, d18}, [r0] 1675 # CHECK: vld3.32 {d16, d17, d18}, [r0] 1677 # CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! 1679 # CHECK: vld3.8 {d17, d19, d21}, [r0, :64]! 1681 # CHECK: vld3.16 {d16, d18, d20}, [r0]! 1683 # CHECK: vld3.16 {d17, d19, d21}, [r0]! 1685 # CHECK: vld3.32 {d16, d18, d20}, [r0]! 1687 # CHECK: vld3.32 {d17, d19, d21}, [r0]! 1727 # CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0] [all …]
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/external/llvm/lib/Target/ARM/ |
D | ARMInstrNEON.td | 908 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> { 927 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", 1208 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt, 1246 IIC_VLD3lnu, "vld3", Dt, 1519 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> { 1542 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm", 7377 def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr", 7380 def VLD3DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr", 7383 def VLD3DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr", 7386 def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr", [all …]
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/external/llvm/test/Transforms/LoopStrengthReduce/ARM/ |
D | ivchain-ARM.ll | 335 %vld3 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8* %add.ptr7, i32 1) 346 %vadd2 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld2, <8 x i8> %vld3) nounwind 347 %vadd3 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld3, <8 x i8> %vld4) nounwind
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