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Searched refs:zeroing (Results 1 – 25 of 48) sorted by relevance

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/external/python/cpython2/Mac/Demo/applescript/Disk_Copy/
DStandard_Suite.py150 class zeroing(aetools.NProperty): class
324 'zeroing' : zeroing,
454 'PZeB' : zeroing,
/external/llvm/test/CodeGen/X86/
DTruncAssertZext.ll2 ; Checks that a zeroing mov is inserted for the trunc/zext pair even when
D2012-12-06-python27-miscompile.ll6 ; Make sure that we are zeroing one memory location at a time using xorl and
Dnontemporal-2.ll10 ; We use xorps for zeroing, so domain information isn't available anymore.
12 ; Scalar versions (zeroing means we can this even for fp types).
/external/llvm/test/CodeGen/AArch64/
Darm64-zero-cycle-zeroing.ll59 ; We used to produce spills+reloads for a Q register with zero cycle zeroing
/external/harfbuzz_ng/
DNEWS189 address "regression" introduced in 1.2.0 when we switched mark zeroing
255 - Change mark zeroing types of most shapers from BY_UNICODE_LATE to
257 - Change mark zeroing of USE shaper from NONE to BY_GDEF_EARLY. That's
558 - Fix mark advance zeroing for Hebrew shaper:
878 - Fix regression with Arabic mark positioning / width-zeroing.
897 - Fix Arabic mark width zeroing regression.
/external/llvm/lib/Target/WebAssembly/
DREADME.txt91 WebAssembly registers are implicitly initialized to zero. Explicit zeroing is
/external/llvm/lib/Target/AArch64/
DAArch64.td53 "Has zero-cycle zeroing instructions">;
/external/llvm/lib/Target/ARM/
DARM.td104 // Cyclone has preferred instructions for zeroing VFP registers, which can
107 "Has zero-cycle zeroing instructions">;
/external/valgrind/
DREADME.aarch64176 ARM64in_VDfromX and ARM64in_VQfromXX: use simple top-half zeroing
/external/libunwind_llvm/src/
DUnwindRegistersSave.S326 @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrFragmentsSIMD.td181 // These are 'extloads' from a scalar to the low element of a vector, zeroing
DREADME.txt1025 We can fold a store into "zeroing a reg". Instead of:
DX86InstrSSE.td328 // Loading from memory automatically zeroing upper bits.
413 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
469 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
544 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
/external/jemalloc/
DChangeLog95 - Fix opt_zero-triggered in-place huge reallocation zeroing. (@jasone)
745 - Fix large calloc() zeroing bugs due to dropping chunk map unzeroed flags.
/external/clang/test/CodeGenObjC/
Darc.m712 // before the zeroing of self.
758 // before the zeroing of self.
/external/llvm/lib/Target/X86/
DX86InstrFragmentsSIMD.td582 // These are 'extloads' from a scalar to the low element of a vector, zeroing
DREADME.txt862 We can fold a store into "zeroing a reg". Instead of:
DX86InstrSSE.td554 // Loading from memory automatically zeroing upper bits.
682 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
716 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
7107 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
/external/swiftshader/third_party/LLVM/lib/Target/
DREADME.txt1394 that bb65 stores to the string, zeroing out the last byte. This means that on
2097 a hole), instead of doing elementwise zeroing.
/external/llvm/lib/Target/
DREADME.txt1351 that bb65 stores to the string, zeroing out the last byte. This means that on
2016 a hole), instead of doing elementwise zeroing.
/external/e2fsprogs/po/
De2fsprogs.pot4961 msgid "while zeroing journal device (block %llu, count %d)"
5618 msgid "while zeroing block %llu at end of filesystem"
Dsr.po5399 msgid "while zeroing journal device (block %llu, count %d)"
6143 msgid "while zeroing block %llu at end of filesystem"
Duk.po5428 msgid "while zeroing journal device (block %llu, count %d)"
6183 msgid "while zeroing block %llu at end of filesystem"
Dzh_CN.po5204 msgid "while zeroing journal device (block %llu, count %d)"
5935 msgid "while zeroing block %llu at end of filesystem"

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